1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <drivers/st/stm32mp1_rcc.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/reset/stm32mp1-resets.h> 14 #include <lib/utils_def.h> 15 #include <lib/xlat_tables/xlat_tables_defs.h> 16 17 #ifndef __ASSEMBLY__ 18 #include <drivers/st/stm32mp1_clk.h> 19 20 #include <boot_api.h> 21 #include <stm32mp_common.h> 22 #include <stm32mp_dt.h> 23 #include <stm32mp_shres_helpers.h> 24 #include <stm32mp1_private.h> 25 #endif 26 27 /******************************************************************************* 28 * STM32MP1 memory map related constants 29 ******************************************************************************/ 30 31 #define STM32MP_SYSRAM_BASE U(0x2FFC0000) 32 #define STM32MP_SYSRAM_SIZE U(0x00040000) 33 34 /* DDR configuration */ 35 #define STM32MP_DDR_BASE U(0xC0000000) 36 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 37 #ifdef AARCH32_SP_OPTEE 38 #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ 39 #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ 40 #endif 41 42 /* DDR power initializations */ 43 #ifndef __ASSEMBLY__ 44 enum ddr_type { 45 STM32MP_DDR3, 46 STM32MP_LPDDR2, 47 }; 48 #endif 49 50 /* Section used inside TF binaries */ 51 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 Ko for param */ 52 /* 256 Octets reserved for header */ 53 #define STM32MP_HEADER_SIZE U(0x00000100) 54 55 #define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \ 56 STM32MP_PARAM_LOAD_SIZE + \ 57 STM32MP_HEADER_SIZE) 58 59 #define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \ 60 (STM32MP_PARAM_LOAD_SIZE + \ 61 STM32MP_HEADER_SIZE)) 62 63 #ifdef AARCH32_SP_OPTEE 64 #define STM32MP_BL32_SIZE U(0) 65 66 #define STM32MP_OPTEE_BASE STM32MP_SYSRAM_BASE 67 68 #define STM32MP_OPTEE_SIZE (STM32MP_DTB_BASE - \ 69 STM32MP_OPTEE_BASE) 70 #else 71 #if STACK_PROTECTOR_ENABLED 72 #define STM32MP_BL32_SIZE U(0x00012000) /* 72 Ko for BL32 */ 73 #else 74 #define STM32MP_BL32_SIZE U(0x00011000) /* 68 Ko for BL32 */ 75 #endif 76 #endif 77 78 #define STM32MP_BL32_BASE (STM32MP_SYSRAM_BASE + \ 79 STM32MP_SYSRAM_SIZE - \ 80 STM32MP_BL32_SIZE) 81 82 #ifdef AARCH32_SP_OPTEE 83 #if STACK_PROTECTOR_ENABLED 84 #define STM32MP_BL2_SIZE U(0x00019000) /* 100 Ko for BL2 */ 85 #else 86 #define STM32MP_BL2_SIZE U(0x00017000) /* 92 Ko for BL2 */ 87 #endif 88 #else 89 #if STACK_PROTECTOR_ENABLED 90 #define STM32MP_BL2_SIZE U(0x00015000) /* 84 Ko for BL2 */ 91 #else 92 #define STM32MP_BL2_SIZE U(0x00013000) /* 76 Ko for BL2 */ 93 #endif 94 #endif 95 96 #define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \ 97 STM32MP_BL2_SIZE) 98 99 /* BL2 and BL32/sp_min require 5 tables */ 100 #define MAX_XLAT_TABLES 5 101 102 /* 103 * MAX_MMAP_REGIONS is usually: 104 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 105 */ 106 #if defined(IMAGE_BL2) 107 #define MAX_MMAP_REGIONS 11 108 #endif 109 #if defined(IMAGE_BL32) 110 #define MAX_MMAP_REGIONS 6 111 #endif 112 113 /* DTB initialization value */ 114 #define STM32MP_DTB_SIZE U(0x00004000) /* 16Ko for DTB */ 115 116 #define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \ 117 STM32MP_DTB_SIZE) 118 119 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) 120 121 /******************************************************************************* 122 * STM32MP1 device/io map related constants (used for MMU) 123 ******************************************************************************/ 124 #define STM32MP1_DEVICE1_BASE U(0x40000000) 125 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 126 127 #define STM32MP1_DEVICE2_BASE U(0x80000000) 128 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 129 130 /******************************************************************************* 131 * STM32MP1 RCC 132 ******************************************************************************/ 133 #define RCC_BASE U(0x50000000) 134 135 /******************************************************************************* 136 * STM32MP1 PWR 137 ******************************************************************************/ 138 #define PWR_BASE U(0x50001000) 139 140 /******************************************************************************* 141 * STM32MP1 GPIO 142 ******************************************************************************/ 143 #define GPIOA_BASE U(0x50002000) 144 #define GPIOB_BASE U(0x50003000) 145 #define GPIOC_BASE U(0x50004000) 146 #define GPIOD_BASE U(0x50005000) 147 #define GPIOE_BASE U(0x50006000) 148 #define GPIOF_BASE U(0x50007000) 149 #define GPIOG_BASE U(0x50008000) 150 #define GPIOH_BASE U(0x50009000) 151 #define GPIOI_BASE U(0x5000A000) 152 #define GPIOJ_BASE U(0x5000B000) 153 #define GPIOK_BASE U(0x5000C000) 154 #define GPIOZ_BASE U(0x54004000) 155 #define GPIO_BANK_OFFSET U(0x1000) 156 157 /* Bank IDs used in GPIO driver API */ 158 #define GPIO_BANK_A U(0) 159 #define GPIO_BANK_B U(1) 160 #define GPIO_BANK_C U(2) 161 #define GPIO_BANK_D U(3) 162 #define GPIO_BANK_E U(4) 163 #define GPIO_BANK_F U(5) 164 #define GPIO_BANK_G U(6) 165 #define GPIO_BANK_H U(7) 166 #define GPIO_BANK_I U(8) 167 #define GPIO_BANK_J U(9) 168 #define GPIO_BANK_K U(10) 169 #define GPIO_BANK_Z U(25) 170 171 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 172 173 /******************************************************************************* 174 * STM32MP1 UART 175 ******************************************************************************/ 176 #define USART1_BASE U(0x5C000000) 177 #define USART2_BASE U(0x4000E000) 178 #define USART3_BASE U(0x4000F000) 179 #define UART4_BASE U(0x40010000) 180 #define UART5_BASE U(0x40011000) 181 #define USART6_BASE U(0x44003000) 182 #define UART7_BASE U(0x40018000) 183 #define UART8_BASE U(0x40019000) 184 #define STM32MP_UART_BAUDRATE U(115200) 185 186 /* For UART crash console */ 187 #define STM32MP_DEBUG_USART_BASE UART4_BASE 188 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ 189 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 190 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE 191 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR 192 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN 193 #define DEBUG_UART_TX_GPIO_PORT 11 194 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 195 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR 196 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI 197 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR 198 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN 199 200 /******************************************************************************* 201 * STM32MP1 TZC (TZ400) 202 ******************************************************************************/ 203 #define STM32MP1_TZC_BASE U(0x5C006000) 204 205 #define STM32MP1_TZC_A7_ID U(0) 206 #define STM32MP1_TZC_M4_ID U(1) 207 #define STM32MP1_TZC_LCD_ID U(3) 208 #define STM32MP1_TZC_GPU_ID U(4) 209 #define STM32MP1_TZC_MDMA_ID U(5) 210 #define STM32MP1_TZC_DMA_ID U(6) 211 #define STM32MP1_TZC_USB_HOST_ID U(7) 212 #define STM32MP1_TZC_USB_OTG_ID U(8) 213 #define STM32MP1_TZC_SDMMC_ID U(9) 214 #define STM32MP1_TZC_ETH_ID U(10) 215 #define STM32MP1_TZC_DAP_ID U(15) 216 217 #define STM32MP1_FILTER_BIT_ALL U(3) 218 219 /******************************************************************************* 220 * STM32MP1 SDMMC 221 ******************************************************************************/ 222 #define STM32MP_SDMMC1_BASE U(0x58005000) 223 #define STM32MP_SDMMC2_BASE U(0x58007000) 224 #define STM32MP_SDMMC3_BASE U(0x48004000) 225 226 #define STM32MP_MMC_INIT_FREQ 400000 /*400 KHz*/ 227 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ 25000000 /*25 MHz*/ 228 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ 50000000 /*50 MHz*/ 229 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ 26000000 /*26 MHz*/ 230 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ 52000000 /*52 MHz*/ 231 232 /******************************************************************************* 233 * STM32MP1 BSEC / OTP 234 ******************************************************************************/ 235 #define STM32MP1_OTP_MAX_ID 0x5FU 236 #define STM32MP1_UPPER_OTP_START 0x20U 237 238 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 239 240 /* OTP offsets */ 241 #define DATA0_OTP U(0) 242 243 /* OTP mask */ 244 /* DATA0 */ 245 #define DATA0_OTP_SECURED BIT(6) 246 247 /******************************************************************************* 248 * STM32MP1 TAMP 249 ******************************************************************************/ 250 #define TAMP_BASE U(0x5C00A000) 251 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 252 253 #if !(defined(__LINKER__) || defined(__ASSEMBLY__)) 254 static inline uint32_t tamp_bkpr(uint32_t idx) 255 { 256 return TAMP_BKP_REGISTER_BASE + (idx << 2); 257 } 258 #endif 259 260 /******************************************************************************* 261 * STM32MP1 DDRCTRL 262 ******************************************************************************/ 263 #define DDRCTRL_BASE U(0x5A003000) 264 265 /******************************************************************************* 266 * STM32MP1 DDRPHYC 267 ******************************************************************************/ 268 #define DDRPHYC_BASE U(0x5A004000) 269 270 /******************************************************************************* 271 * STM32MP1 I2C4 272 ******************************************************************************/ 273 #define I2C4_BASE U(0x5C002000) 274 275 /******************************************************************************* 276 * Device Tree defines 277 ******************************************************************************/ 278 #define DT_PWR_COMPAT "st,stm32mp1-pwr" 279 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" 280 281 #endif /* STM32MP1_DEF_H */ 282