xref: /rk3399_ARM-atf/plat/st/stm32mp1/stm32mp1_dbgmcu.c (revision 73680c230f8503a8e0f625834bc987b90e065b03)
1*73680c23SYann Gautier /*
2*73680c23SYann Gautier  * Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved
3*73680c23SYann Gautier  *
4*73680c23SYann Gautier  * SPDX-License-Identifier: BSD-3-Clause
5*73680c23SYann Gautier  */
6*73680c23SYann Gautier 
7*73680c23SYann Gautier #include <errno.h>
8*73680c23SYann Gautier 
9*73680c23SYann Gautier #include <platform_def.h>
10*73680c23SYann Gautier 
11*73680c23SYann Gautier #include <common/debug.h>
12*73680c23SYann Gautier #include <drivers/st/bsec.h>
13*73680c23SYann Gautier #include <drivers/st/stm32mp1_rcc.h>
14*73680c23SYann Gautier #include <lib/mmio.h>
15*73680c23SYann Gautier #include <lib/utils_def.h>
16*73680c23SYann Gautier 
17*73680c23SYann Gautier #include <stm32mp1_dbgmcu.h>
18*73680c23SYann Gautier 
19*73680c23SYann Gautier #define DBGMCU_APB4FZ1		U(0x2C)
20*73680c23SYann Gautier #define DBGMCU_APB4FZ1_IWDG2	BIT(2)
21*73680c23SYann Gautier 
22*73680c23SYann Gautier static uintptr_t get_rcc_base(void)
23*73680c23SYann Gautier {
24*73680c23SYann Gautier 	/* This is called before stm32mp_rcc_base() is available */
25*73680c23SYann Gautier 	return RCC_BASE;
26*73680c23SYann Gautier }
27*73680c23SYann Gautier 
28*73680c23SYann Gautier static int stm32mp1_dbgmcu_init(void)
29*73680c23SYann Gautier {
30*73680c23SYann Gautier 	uint32_t dbg_conf;
31*73680c23SYann Gautier 	uintptr_t rcc_base = get_rcc_base();
32*73680c23SYann Gautier 
33*73680c23SYann Gautier 	dbg_conf = bsec_read_debug_conf();
34*73680c23SYann Gautier 
35*73680c23SYann Gautier 	if ((dbg_conf & BSEC_DBGSWGEN) == 0U) {
36*73680c23SYann Gautier 		uint32_t result = bsec_write_debug_conf(dbg_conf |
37*73680c23SYann Gautier 							BSEC_DBGSWGEN);
38*73680c23SYann Gautier 
39*73680c23SYann Gautier 		if (result != BSEC_OK) {
40*73680c23SYann Gautier 			ERROR("Error enabling DBGSWGEN\n");
41*73680c23SYann Gautier 			return -1;
42*73680c23SYann Gautier 		}
43*73680c23SYann Gautier 	}
44*73680c23SYann Gautier 
45*73680c23SYann Gautier 	mmio_setbits_32(rcc_base + RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
46*73680c23SYann Gautier 
47*73680c23SYann Gautier 	return 0;
48*73680c23SYann Gautier }
49*73680c23SYann Gautier 
50*73680c23SYann Gautier int stm32mp1_dbgmcu_freeze_iwdg2(void)
51*73680c23SYann Gautier {
52*73680c23SYann Gautier 	uint32_t dbg_conf;
53*73680c23SYann Gautier 
54*73680c23SYann Gautier 	if (stm32mp1_dbgmcu_init() != 0) {
55*73680c23SYann Gautier 		return -EPERM;
56*73680c23SYann Gautier 	}
57*73680c23SYann Gautier 
58*73680c23SYann Gautier 	dbg_conf = bsec_read_debug_conf();
59*73680c23SYann Gautier 
60*73680c23SYann Gautier 	if ((dbg_conf & (BSEC_SPIDEN | BSEC_SPINDEN)) != 0U) {
61*73680c23SYann Gautier 		mmio_setbits_32(DBGMCU_BASE + DBGMCU_APB4FZ1,
62*73680c23SYann Gautier 				DBGMCU_APB4FZ1_IWDG2);
63*73680c23SYann Gautier 	}
64*73680c23SYann Gautier 
65*73680c23SYann Gautier 	return 0;
66*73680c23SYann Gautier }
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