1*f74cbc93SYann Gautier/* 2*f74cbc93SYann Gautier * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*f74cbc93SYann Gautier * 4*f74cbc93SYann Gautier * SPDX-License-Identifier: BSD-3-Clause 5*f74cbc93SYann Gautier */ 6*f74cbc93SYann Gautier 7*f74cbc93SYann Gautier#ifndef __STM32MP1_LD_S__ 8*f74cbc93SYann Gautier#define __STM32MP1_LD_S__ 9*f74cbc93SYann Gautier#include <platform_def.h> 10*f74cbc93SYann Gautier#include <xlat_tables_defs.h> 11*f74cbc93SYann Gautier 12*f74cbc93SYann GautierOUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 13*f74cbc93SYann GautierOUTPUT_ARCH(PLATFORM_LINKER_ARCH) 14*f74cbc93SYann Gautier 15*f74cbc93SYann GautierENTRY(__BL2_IMAGE_START__) 16*f74cbc93SYann Gautier 17*f74cbc93SYann GautierMEMORY { 18*f74cbc93SYann Gautier HEADER (rw) : ORIGIN = 0x00000000, LENGTH = 0x3000 19*f74cbc93SYann Gautier RAM (rwx) : ORIGIN = STM32MP1_BINARY_BASE, LENGTH = STM32MP1_BINARY_SIZE 20*f74cbc93SYann Gautier} 21*f74cbc93SYann Gautier 22*f74cbc93SYann GautierSECTIONS 23*f74cbc93SYann Gautier{ 24*f74cbc93SYann Gautier /* 25*f74cbc93SYann Gautier * TF mapping must conform to ROM code specification. 26*f74cbc93SYann Gautier */ 27*f74cbc93SYann Gautier .header : { 28*f74cbc93SYann Gautier __HEADER_START__ = .; 29*f74cbc93SYann Gautier KEEP(*(.header)) 30*f74cbc93SYann Gautier . = ALIGN(4); 31*f74cbc93SYann Gautier __HEADER_END__ = .; 32*f74cbc93SYann Gautier } >HEADER 33*f74cbc93SYann Gautier 34*f74cbc93SYann Gautier . = STM32MP1_BINARY_BASE; 35*f74cbc93SYann Gautier .data . : { 36*f74cbc93SYann Gautier . = ALIGN(PAGE_SIZE); 37*f74cbc93SYann Gautier __DATA_START__ = .; 38*f74cbc93SYann Gautier *(.data*) 39*f74cbc93SYann Gautier 40*f74cbc93SYann Gautier /* 41*f74cbc93SYann Gautier * dtb. 42*f74cbc93SYann Gautier * The strongest and only alignment contraint is MMU 4K page. 43*f74cbc93SYann Gautier * Indeed as images below will be removed, 4K pages will be re-used. 44*f74cbc93SYann Gautier */ 45*f74cbc93SYann Gautier . = ( STM32MP1_DTB_BASE - STM32MP1_BINARY_BASE ); 46*f74cbc93SYann Gautier __DTB_IMAGE_START__ = .; 47*f74cbc93SYann Gautier *(.dtb_image*) 48*f74cbc93SYann Gautier __DTB_IMAGE_END__ = .; 49*f74cbc93SYann Gautier 50*f74cbc93SYann Gautier /* 51*f74cbc93SYann Gautier * bl2. 52*f74cbc93SYann Gautier * The strongest and only alignment contraint is MMU 4K page. 53*f74cbc93SYann Gautier * Indeed as images below will be removed, 4K pages will be re-used. 54*f74cbc93SYann Gautier */ 55*f74cbc93SYann Gautier . = ( STM32MP1_BL2_BASE - STM32MP1_BINARY_BASE ); 56*f74cbc93SYann Gautier __BL2_IMAGE_START__ = .; 57*f74cbc93SYann Gautier *(.bl2_image*) 58*f74cbc93SYann Gautier __BL2_IMAGE_END__ = .; 59*f74cbc93SYann Gautier 60*f74cbc93SYann Gautier /* 61*f74cbc93SYann Gautier * bl32 will be settled by bl2. 62*f74cbc93SYann Gautier * The strongest and only alignment constraint is 8 words to simplify 63*f74cbc93SYann Gautier * memraise8 assembly code. 64*f74cbc93SYann Gautier */ 65*f74cbc93SYann Gautier . = ( STM32MP1_BL32_BASE - STM32MP1_BINARY_BASE ); 66*f74cbc93SYann Gautier __BL32_IMAGE_START__ = .; 67*f74cbc93SYann Gautier *(.bl32_image*) 68*f74cbc93SYann Gautier __BL32_IMAGE_END__ = .; 69*f74cbc93SYann Gautier 70*f74cbc93SYann Gautier __DATA_END__ = .; 71*f74cbc93SYann Gautier } >RAM 72*f74cbc93SYann Gautier 73*f74cbc93SYann Gautier __TF_END__ = .; 74*f74cbc93SYann Gautier 75*f74cbc93SYann Gautier} 76*f74cbc93SYann Gautier#endif /*__STM32MP1_LD_S__*/ 77