1f74cbc93SYann Gautier/* 2*1d204ee4SYann Gautier * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3f74cbc93SYann Gautier * 4f74cbc93SYann Gautier * SPDX-License-Identifier: BSD-3-Clause 5f74cbc93SYann Gautier */ 6f74cbc93SYann Gautier 7c3cf06f1SAntonio Nino Diaz#ifndef STM32MP1_LD_S 8c3cf06f1SAntonio Nino Diaz#define STM32MP1_LD_S 9c3cf06f1SAntonio Nino Diaz 1009d40e0eSAntonio Nino Diaz#include <lib/xlat_tables/xlat_tables_defs.h> 11f74cbc93SYann Gautier#include <platform_def.h> 12f74cbc93SYann Gautier 13f74cbc93SYann GautierOUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 14f74cbc93SYann GautierOUTPUT_ARCH(PLATFORM_LINKER_ARCH) 15f74cbc93SYann Gautier 16f74cbc93SYann GautierENTRY(__BL2_IMAGE_START__) 17f74cbc93SYann Gautier 18f74cbc93SYann GautierMEMORY { 19f74cbc93SYann Gautier HEADER (rw) : ORIGIN = 0x00000000, LENGTH = 0x3000 203f9c9784SYann Gautier RAM (rwx) : ORIGIN = STM32MP_BINARY_BASE, LENGTH = STM32MP_BINARY_SIZE 21f74cbc93SYann Gautier} 22f74cbc93SYann Gautier 23f74cbc93SYann GautierSECTIONS 24f74cbc93SYann Gautier{ 25f74cbc93SYann Gautier /* 26f74cbc93SYann Gautier * TF mapping must conform to ROM code specification. 27f74cbc93SYann Gautier */ 28f74cbc93SYann Gautier .header : { 29f74cbc93SYann Gautier __HEADER_START__ = .; 30f74cbc93SYann Gautier KEEP(*(.header)) 31f74cbc93SYann Gautier . = ALIGN(4); 32f74cbc93SYann Gautier __HEADER_END__ = .; 33f74cbc93SYann Gautier } >HEADER 34f74cbc93SYann Gautier 353f9c9784SYann Gautier . = STM32MP_BINARY_BASE; 36f74cbc93SYann Gautier .data . : { 37f74cbc93SYann Gautier . = ALIGN(PAGE_SIZE); 38f74cbc93SYann Gautier __DATA_START__ = .; 39f74cbc93SYann Gautier *(.data*) 40f74cbc93SYann Gautier 41f74cbc93SYann Gautier /* 42f74cbc93SYann Gautier * dtb. 43f74cbc93SYann Gautier * The strongest and only alignment contraint is MMU 4K page. 44f74cbc93SYann Gautier * Indeed as images below will be removed, 4K pages will be re-used. 45f74cbc93SYann Gautier */ 46*1d204ee4SYann Gautier#if STM32MP_USE_STM32IMAGE 473f9c9784SYann Gautier . = ( STM32MP_DTB_BASE - STM32MP_BINARY_BASE ); 48*1d204ee4SYann Gautier#else 49*1d204ee4SYann Gautier . = ( STM32MP_BL2_DTB_BASE - STM32MP_BINARY_BASE ); 50*1d204ee4SYann Gautier#endif /* STM32MP_USE_STM32IMAGE */ 51f74cbc93SYann Gautier __DTB_IMAGE_START__ = .; 52f74cbc93SYann Gautier *(.dtb_image*) 53f74cbc93SYann Gautier __DTB_IMAGE_END__ = .; 54f74cbc93SYann Gautier 55f74cbc93SYann Gautier /* 56f74cbc93SYann Gautier * bl2. 57f74cbc93SYann Gautier * The strongest and only alignment contraint is MMU 4K page. 58f74cbc93SYann Gautier * Indeed as images below will be removed, 4K pages will be re-used. 59f74cbc93SYann Gautier */ 603f9c9784SYann Gautier . = ( STM32MP_BL2_BASE - STM32MP_BINARY_BASE ); 61f74cbc93SYann Gautier __BL2_IMAGE_START__ = .; 62f74cbc93SYann Gautier *(.bl2_image*) 63f74cbc93SYann Gautier __BL2_IMAGE_END__ = .; 64f74cbc93SYann Gautier 65*1d204ee4SYann Gautier#if STM32MP_USE_STM32IMAGE && !defined(AARCH32_SP_OPTEE) 66f74cbc93SYann Gautier /* 67f74cbc93SYann Gautier * bl32 will be settled by bl2. 68f74cbc93SYann Gautier * The strongest and only alignment constraint is 8 words to simplify 69f74cbc93SYann Gautier * memraise8 assembly code. 70f74cbc93SYann Gautier */ 713f9c9784SYann Gautier . = ( STM32MP_BL32_BASE - STM32MP_BINARY_BASE ); 72f74cbc93SYann Gautier __BL32_IMAGE_START__ = .; 73f74cbc93SYann Gautier *(.bl32_image*) 74f74cbc93SYann Gautier __BL32_IMAGE_END__ = .; 75*1d204ee4SYann Gautier#endif /* STM32MP_USE_STM32IMAGE && !defined(AARCH32_SP_OPTEE) */ 76f74cbc93SYann Gautier 77f74cbc93SYann Gautier __DATA_END__ = .; 78f74cbc93SYann Gautier } >RAM 79f74cbc93SYann Gautier 80f74cbc93SYann Gautier __TF_END__ = .; 81f74cbc93SYann Gautier 82f74cbc93SYann Gautier} 83c3cf06f1SAntonio Nino Diaz#endif /* STM32MP1_LD_S */ 84