1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/tzc400.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/st/stm32_console.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 #include <dt-bindings/clock/stm32mp1-clks.h> 21 #include <lib/el3_runtime/context_mgmt.h> 22 #include <lib/mmio.h> 23 #include <lib/xlat_tables/xlat_tables_v2.h> 24 #include <plat/common/platform.h> 25 26 #include <platform_sp_min.h> 27 #include <stm32mp1_dt.h> 28 #include <stm32mp1_private.h> 29 30 /****************************************************************************** 31 * Placeholder variables for copying the arguments that have been passed to 32 * BL32 from BL2. 33 ******************************************************************************/ 34 static entry_point_info_t bl33_image_ep_info; 35 36 static struct console_stm32 console; 37 38 /******************************************************************************* 39 * Interrupt handler for FIQ (secure IRQ) 40 ******************************************************************************/ 41 void sp_min_plat_fiq_handler(uint32_t id) 42 { 43 switch (id) { 44 case STM32MP1_IRQ_TZC400: 45 ERROR("STM32MP1_IRQ_TZC400 generated\n"); 46 panic(); 47 break; 48 case STM32MP1_IRQ_AXIERRIRQ: 49 ERROR("STM32MP1_IRQ_AXIERRIRQ generated\n"); 50 panic(); 51 break; 52 default: 53 ERROR("SECURE IT handler not define for it : %i", id); 54 break; 55 } 56 } 57 58 /******************************************************************************* 59 * Return a pointer to the 'entry_point_info' structure of the next image for 60 * the security state specified. BL33 corresponds to the non-secure image type 61 * while BL32 corresponds to the secure image type. A NULL pointer is returned 62 * if the image does not exist. 63 ******************************************************************************/ 64 entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) 65 { 66 entry_point_info_t *next_image_info; 67 68 next_image_info = &bl33_image_ep_info; 69 70 if (next_image_info->pc == 0U) { 71 return NULL; 72 } 73 74 return next_image_info; 75 } 76 77 /******************************************************************************* 78 * Perform any BL32 specific platform actions. 79 ******************************************************************************/ 80 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, 81 u_register_t arg2, u_register_t arg3) 82 { 83 struct dt_node_info dt_dev_info; 84 int result; 85 bl_params_t *params_from_bl2 = (bl_params_t *)arg0; 86 87 /* Imprecise aborts can be masked in NonSecure */ 88 write_scr(read_scr() | SCR_AW_BIT); 89 90 assert(params_from_bl2 != NULL); 91 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 92 assert(params_from_bl2->h.version >= VERSION_2); 93 94 bl_params_node_t *bl_params = params_from_bl2->head; 95 96 /* 97 * Copy BL33 entry point information. 98 * They are stored in Secure RAM, in BL2's address space. 99 */ 100 while (bl_params != NULL) { 101 if (bl_params->image_id == BL33_IMAGE_ID) { 102 bl33_image_ep_info = *bl_params->ep_info; 103 break; 104 } 105 106 bl_params = bl_params->next_params_info; 107 } 108 109 if (dt_open_and_check() < 0) { 110 panic(); 111 } 112 113 if (stm32mp1_clk_probe() < 0) { 114 panic(); 115 } 116 117 result = dt_get_stdout_uart_info(&dt_dev_info); 118 119 if ((result > 0) && dt_dev_info.status) { 120 if (console_stm32_register(dt_dev_info.base, 0, 121 STM32MP1_UART_BAUDRATE, &console) == 122 0) { 123 panic(); 124 } 125 } 126 } 127 128 /******************************************************************************* 129 * Initialize the MMU, security and the GIC. 130 ******************************************************************************/ 131 void sp_min_platform_setup(void) 132 { 133 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 134 BL_CODE_END - BL_CODE_BASE, 135 MT_CODE | MT_SECURE); 136 137 configure_mmu(); 138 139 /* Initialize tzc400 after DDR initialization */ 140 stm32mp1_security_setup(); 141 142 generic_delay_timer_init(); 143 144 stm32mp1_gic_init(); 145 } 146 147 void sp_min_plat_arch_setup(void) 148 { 149 } 150