1 /* 2 * Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <arch_helpers.h> 11 #include <bl32/sp_min/platform_sp_min.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <context.h> 15 #include <drivers/arm/gicv2.h> 16 #include <drivers/arm/tzc400.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/st/bsec.h> 19 #include <drivers/st/etzpc.h> 20 #include <drivers/st/stm32_gpio.h> 21 #include <drivers/st/stm32_iwdg.h> 22 #include <drivers/st/stm32mp1_clk.h> 23 #include <dt-bindings/clock/stm32mp1-clks.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/mmio.h> 26 #include <lib/xlat_tables/xlat_tables_v2.h> 27 #include <plat/common/platform.h> 28 29 #include <platform_def.h> 30 31 /****************************************************************************** 32 * Placeholder variables for copying the arguments that have been passed to 33 * BL32 from BL2. 34 ******************************************************************************/ 35 static entry_point_info_t bl33_image_ep_info; 36 37 /******************************************************************************* 38 * Interrupt handler for FIQ (secure IRQ) 39 ******************************************************************************/ 40 void sp_min_plat_fiq_handler(uint32_t id) 41 { 42 (void)plat_crash_console_init(); 43 44 switch (id & INT_ID_MASK) { 45 case STM32MP1_IRQ_TZC400: 46 tzc400_init(STM32MP1_TZC_BASE); 47 (void)tzc400_it_handler(); 48 panic(); 49 break; 50 case STM32MP1_IRQ_AXIERRIRQ: 51 ERROR("STM32MP1_IRQ_AXIERRIRQ generated\n"); 52 panic(); 53 break; 54 default: 55 ERROR("SECURE IT handler not define for it : %u\n", id); 56 break; 57 } 58 } 59 60 /******************************************************************************* 61 * Return a pointer to the 'entry_point_info' structure of the next image for 62 * the security state specified. BL33 corresponds to the non-secure image type 63 * while BL32 corresponds to the secure image type. A NULL pointer is returned 64 * if the image does not exist. 65 ******************************************************************************/ 66 entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) 67 { 68 entry_point_info_t *next_image_info; 69 70 next_image_info = &bl33_image_ep_info; 71 72 if (next_image_info->pc == 0U) { 73 return NULL; 74 } 75 76 return next_image_info; 77 } 78 79 CASSERT((STM32MP_SEC_SYSRAM_BASE == STM32MP_SYSRAM_BASE) && 80 ((STM32MP_SEC_SYSRAM_BASE + STM32MP_SEC_SYSRAM_SIZE) <= 81 (STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE)), 82 assert_secure_sysram_fits_at_begining_of_sysram); 83 84 #ifdef STM32MP_NS_SYSRAM_BASE 85 CASSERT((STM32MP_NS_SYSRAM_BASE >= STM32MP_SEC_SYSRAM_BASE) && 86 ((STM32MP_NS_SYSRAM_BASE + STM32MP_NS_SYSRAM_SIZE) == 87 (STM32MP_SYSRAM_BASE + STM32MP_SYSRAM_SIZE)), 88 assert_non_secure_sysram_fits_at_end_of_sysram); 89 90 CASSERT((STM32MP_NS_SYSRAM_BASE & (PAGE_SIZE_4KB - U(1))) == 0U, 91 assert_non_secure_sysram_base_is_4kbyte_aligned); 92 93 #define TZMA1_SECURE_RANGE \ 94 (((STM32MP_NS_SYSRAM_BASE - STM32MP_SYSRAM_BASE) >> FOUR_KB_SHIFT) - 1U) 95 #else 96 #define TZMA1_SECURE_RANGE STM32MP1_ETZPC_TZMA_ALL_SECURE 97 #endif /* STM32MP_NS_SYSRAM_BASE */ 98 #define TZMA0_SECURE_RANGE STM32MP1_ETZPC_TZMA_ALL_SECURE 99 100 static void stm32mp1_etzpc_early_setup(void) 101 { 102 if (etzpc_init() != 0) { 103 panic(); 104 } 105 106 etzpc_configure_tzma(STM32MP1_ETZPC_TZMA_ROM, TZMA0_SECURE_RANGE); 107 etzpc_configure_tzma(STM32MP1_ETZPC_TZMA_SYSRAM, TZMA1_SECURE_RANGE); 108 } 109 110 /******************************************************************************* 111 * Perform any BL32 specific platform actions. 112 ******************************************************************************/ 113 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, 114 u_register_t arg2, u_register_t arg3) 115 { 116 bl_params_t *params_from_bl2 = (bl_params_t *)arg0; 117 uintptr_t dt_addr = arg1; 118 119 /* Imprecise aborts can be masked in NonSecure */ 120 write_scr(read_scr() | SCR_AW_BIT); 121 122 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 123 BL_CODE_END - BL_CODE_BASE, 124 MT_CODE | MT_SECURE); 125 126 configure_mmu(); 127 128 assert(params_from_bl2 != NULL); 129 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 130 assert(params_from_bl2->h.version >= VERSION_2); 131 132 bl_params_node_t *bl_params = params_from_bl2->head; 133 134 /* 135 * Copy BL33 entry point information. 136 * They are stored in Secure RAM, in BL2's address space. 137 */ 138 while (bl_params != NULL) { 139 if (bl_params->image_id == BL33_IMAGE_ID) { 140 bl33_image_ep_info = *bl_params->ep_info; 141 /* 142 * Check if hw_configuration is given to BL32 and 143 * share it to BL33. 144 */ 145 if (arg2 != 0U) { 146 bl33_image_ep_info.args.arg0 = 0U; 147 bl33_image_ep_info.args.arg1 = 0U; 148 bl33_image_ep_info.args.arg2 = arg2; 149 } 150 151 break; 152 } 153 154 bl_params = bl_params->next_params_info; 155 } 156 157 if (dt_open_and_check(dt_addr) < 0) { 158 panic(); 159 } 160 161 if (bsec_probe() != 0) { 162 panic(); 163 } 164 165 if (stm32mp1_clk_probe() < 0) { 166 panic(); 167 } 168 169 (void)stm32mp_uart_console_setup(); 170 171 stm32mp1_etzpc_early_setup(); 172 } 173 174 /******************************************************************************* 175 * Initialize the MMU, security and the GIC. 176 ******************************************************************************/ 177 void sp_min_platform_setup(void) 178 { 179 generic_delay_timer_init(); 180 181 stm32mp_gic_init(); 182 183 /* Disable MCU subsystem protection */ 184 stm32mp1_clk_mcuss_protect(false); 185 186 if (stm32_iwdg_init() < 0) { 187 panic(); 188 } 189 190 stm32mp_lock_periph_registering(); 191 192 stm32mp1_init_scmi_server(); 193 } 194 195 void sp_min_plat_arch_setup(void) 196 { 197 } 198