1 /* 2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <platform_def.h> 8 9 #include <common/bl_common.h> 10 #include <common/desc_image_load.h> 11 #include <plat/common/platform.h> 12 13 /******************************************************************************* 14 * Following descriptor provides BL image/ep information that gets used 15 * by BL2 to load the images and also subset of this information is 16 * passed to next BL image. The image loading sequence is managed by 17 * populating the images in required loading order. The image execution 18 * sequence is managed by populating the `next_handoff_image_id` with 19 * the next executable image id. 20 ******************************************************************************/ 21 static bl_mem_params_node_t bl2_mem_params_descs[] = { 22 /* Fill BL32 related information */ 23 { 24 .image_id = BL32_IMAGE_ID, 25 26 SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, 27 VERSION_2, entry_point_info_t, 28 SECURE | EXECUTABLE | EP_FIRST_EXE), 29 30 #if !defined(AARCH32_SP_OPTEE) 31 .ep_info.pc = BL32_BASE, 32 #endif 33 .ep_info.spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM, 34 SPSR_E_LITTLE, 35 DISABLE_ALL_EXCEPTIONS), 36 37 SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, 38 VERSION_2, image_info_t, 39 IMAGE_ATTRIB_PLAT_SETUP), 40 #if defined(AARCH32_SP_OPTEE) 41 /* optee header is loaded in SYSRAM above BL2 */ 42 .image_info.image_base = STM32MP_OPTEE_BASE, 43 .image_info.image_max_size = STM32MP_OPTEE_SIZE, 44 #else 45 .image_info.image_base = BL32_BASE, 46 .image_info.image_max_size = BL32_LIMIT - BL32_BASE, 47 #endif 48 .next_handoff_image_id = BL33_IMAGE_ID, 49 }, 50 51 #if defined(AARCH32_SP_OPTEE) 52 /* Fill BL32 external 1 image related information */ 53 { 54 .image_id = BL32_EXTRA1_IMAGE_ID, 55 56 SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, 57 VERSION_2, entry_point_info_t, 58 SECURE | NON_EXECUTABLE), 59 60 SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, 61 VERSION_2, image_info_t, 62 IMAGE_ATTRIB_SKIP_LOADING), 63 64 .next_handoff_image_id = INVALID_IMAGE_ID, 65 }, 66 /* Fill BL32 external 2 image related information */ 67 { 68 .image_id = BL32_EXTRA2_IMAGE_ID, 69 70 SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, 71 VERSION_2, entry_point_info_t, 72 SECURE | NON_EXECUTABLE), 73 74 SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, 75 VERSION_2, image_info_t, 76 IMAGE_ATTRIB_SKIP_LOADING), 77 78 .next_handoff_image_id = INVALID_IMAGE_ID, 79 }, 80 #endif /* AARCH32_SP_OPTEE */ 81 82 /* Fill BL33 related information */ 83 { 84 .image_id = BL33_IMAGE_ID, 85 86 SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, 87 VERSION_2, entry_point_info_t, 88 NON_SECURE | EXECUTABLE), 89 90 .ep_info.pc = PLAT_STM32MP_NS_IMAGE_OFFSET, 91 .ep_info.spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM, 92 SPSR_E_LITTLE, 93 DISABLE_ALL_EXCEPTIONS), 94 95 SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, 96 VERSION_2, image_info_t, 0), 97 98 .image_info.image_base = PLAT_STM32MP_NS_IMAGE_OFFSET, 99 .image_info.image_max_size = STM32MP_DDR_MAX_SIZE - 100 (PLAT_STM32MP_NS_IMAGE_OFFSET - STM32MP_DDR_BASE), 101 102 .next_handoff_image_id = INVALID_IMAGE_ID, 103 } 104 }; 105 106 REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs) 107