1*eafe0eb0SEtienne Carriere /* 2*eafe0eb0SEtienne Carriere * Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved 3*eafe0eb0SEtienne Carriere * 4*eafe0eb0SEtienne Carriere * SPDX-License-Identifier: BSD-3-Clause 5*eafe0eb0SEtienne Carriere */ 6*eafe0eb0SEtienne Carriere 7*eafe0eb0SEtienne Carriere #ifndef STM32MP1_SHARED_RESOURCES_H 8*eafe0eb0SEtienne Carriere #define STM32MP1_SHARED_RESOURCES_H 9*eafe0eb0SEtienne Carriere 10*eafe0eb0SEtienne Carriere #include <stm32mp_shared_resources.h> 11*eafe0eb0SEtienne Carriere 12*eafe0eb0SEtienne Carriere #define STM32MP1_SHRES_GPIOZ(i) (STM32MP1_SHRES_GPIOZ_0 + (i)) 13*eafe0eb0SEtienne Carriere 14*eafe0eb0SEtienne Carriere enum stm32mp_shres { 15*eafe0eb0SEtienne Carriere STM32MP1_SHRES_CRYP1, 16*eafe0eb0SEtienne Carriere STM32MP1_SHRES_GPIOZ_0, 17*eafe0eb0SEtienne Carriere STM32MP1_SHRES_GPIOZ_1, 18*eafe0eb0SEtienne Carriere STM32MP1_SHRES_GPIOZ_2, 19*eafe0eb0SEtienne Carriere STM32MP1_SHRES_GPIOZ_3, 20*eafe0eb0SEtienne Carriere STM32MP1_SHRES_GPIOZ_4, 21*eafe0eb0SEtienne Carriere STM32MP1_SHRES_GPIOZ_5, 22*eafe0eb0SEtienne Carriere STM32MP1_SHRES_GPIOZ_6, 23*eafe0eb0SEtienne Carriere STM32MP1_SHRES_GPIOZ_7, 24*eafe0eb0SEtienne Carriere STM32MP1_SHRES_HASH1, 25*eafe0eb0SEtienne Carriere STM32MP1_SHRES_I2C4, 26*eafe0eb0SEtienne Carriere STM32MP1_SHRES_I2C6, 27*eafe0eb0SEtienne Carriere STM32MP1_SHRES_IWDG1, 28*eafe0eb0SEtienne Carriere STM32MP1_SHRES_MCU, 29*eafe0eb0SEtienne Carriere STM32MP1_SHRES_MDMA, 30*eafe0eb0SEtienne Carriere STM32MP1_SHRES_PLL3, 31*eafe0eb0SEtienne Carriere STM32MP1_SHRES_RNG1, 32*eafe0eb0SEtienne Carriere STM32MP1_SHRES_RTC, 33*eafe0eb0SEtienne Carriere STM32MP1_SHRES_SPI6, 34*eafe0eb0SEtienne Carriere STM32MP1_SHRES_USART1, 35*eafe0eb0SEtienne Carriere 36*eafe0eb0SEtienne Carriere STM32MP1_SHRES_COUNT 37*eafe0eb0SEtienne Carriere }; 38*eafe0eb0SEtienne Carriere #endif /* STM32MP1_SHARED_RESOURCES_H */ 39