1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <drivers/arm/gic_common.h> 12 #include <lib/utils_def.h> 13 #include <plat/common/common_def.h> 14 15 #include "../stm32mp1_def.h" 16 17 /******************************************************************************* 18 * Generic platform constants 19 ******************************************************************************/ 20 21 /* Size of cacheable stacks */ 22 #if defined(IMAGE_BL32) 23 #define PLATFORM_STACK_SIZE 0x600 24 #else 25 #define PLATFORM_STACK_SIZE 0xC00 26 #endif 27 28 #ifdef AARCH32_SP_OPTEE 29 #define OPTEE_HEADER_IMAGE_NAME "teeh" 30 #define OPTEE_PAGED_IMAGE_NAME "teed" 31 #define OPTEE_PAGER_IMAGE_NAME "teex" 32 #define OPTEE_HEADER_BINARY_TYPE U(0x20) 33 #define OPTEE_PAGER_BINARY_TYPE U(0x21) 34 #define OPTEE_PAGED_BINARY_TYPE U(0x22) 35 #endif 36 37 /* SSBL = second stage boot loader */ 38 #define BL33_IMAGE_NAME "ssbl" 39 #define BL33_BINARY_TYPE U(0x0) 40 41 #define STM32MP_PRIMARY_CPU U(0x0) 42 #define STM32MP_SECONDARY_CPU U(0x1) 43 44 #define PLATFORM_CLUSTER_COUNT ULL(1) 45 #define PLATFORM_CLUSTER0_CORE_COUNT U(2) 46 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 47 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 48 PLATFORM_CLUSTER0_CORE_COUNT) 49 #define PLATFORM_MAX_CPUS_PER_CLUSTER 2 50 51 #define MAX_IO_DEVICES U(4) 52 #define MAX_IO_HANDLES U(4) 53 #define MAX_IO_BLOCK_DEVICES U(1) 54 55 /******************************************************************************* 56 * BL2 specific defines. 57 ******************************************************************************/ 58 /* 59 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 60 * size plus a little space for growth. 61 */ 62 #define BL2_BASE STM32MP_BL2_BASE 63 #define BL2_LIMIT (STM32MP_BL2_BASE + \ 64 STM32MP_BL2_SIZE) 65 66 /******************************************************************************* 67 * BL32 specific defines. 68 ******************************************************************************/ 69 #ifndef AARCH32_SP_OPTEE 70 #define BL32_BASE STM32MP_BL32_BASE 71 #define BL32_LIMIT (STM32MP_BL32_BASE + \ 72 STM32MP_BL32_SIZE) 73 #endif 74 75 /******************************************************************************* 76 * BL33 specific defines. 77 ******************************************************************************/ 78 #define BL33_BASE STM32MP_BL33_BASE 79 80 /* 81 * Load address of BL33 for this platform port 82 */ 83 #define PLAT_STM32MP_NS_IMAGE_OFFSET BL33_BASE 84 85 /******************************************************************************* 86 * DTB specific defines. 87 ******************************************************************************/ 88 #define DTB_BASE STM32MP_DTB_BASE 89 #define DTB_LIMIT (STM32MP_DTB_BASE + \ 90 STM32MP_DTB_SIZE) 91 92 /******************************************************************************* 93 * Platform specific page table and MMU setup constants 94 ******************************************************************************/ 95 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) 96 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) 97 98 /******************************************************************************* 99 * Declarations and constants to access the mailboxes safely. Each mailbox is 100 * aligned on the biggest cache line size in the platform. This is known only 101 * to the platform as it might have a combination of integrated and external 102 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 103 * line at any cache level. They could belong to different cpus/clusters & 104 * get written while being protected by different locks causing corruption of 105 * a valid mailbox address. 106 ******************************************************************************/ 107 #define CACHE_WRITEBACK_SHIFT 6 108 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 109 110 /* 111 * Secure Interrupt: based on the standard ARM mapping 112 */ 113 #define ARM_IRQ_SEC_PHY_TIMER U(29) 114 115 #define ARM_IRQ_SEC_SGI_0 U(8) 116 #define ARM_IRQ_SEC_SGI_1 U(9) 117 #define ARM_IRQ_SEC_SGI_2 U(10) 118 #define ARM_IRQ_SEC_SGI_3 U(11) 119 #define ARM_IRQ_SEC_SGI_4 U(12) 120 #define ARM_IRQ_SEC_SGI_5 U(13) 121 #define ARM_IRQ_SEC_SGI_6 U(14) 122 #define ARM_IRQ_SEC_SGI_7 U(15) 123 124 #define STM32MP1_IRQ_TZC400 U(36) 125 #define STM32MP1_IRQ_TAMPSERRS U(229) 126 #define STM32MP1_IRQ_AXIERRIRQ U(244) 127 128 /* 129 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 130 * terminology. On a GICv2 system or mode, the lists will be merged and treated 131 * as Group 0 interrupts. 132 */ 133 #define PLATFORM_G1S_PROPS(grp) \ 134 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \ 135 GIC_HIGHEST_SEC_PRIORITY, \ 136 grp, GIC_INTR_CFG_LEVEL), \ 137 INTR_PROP_DESC(STM32MP1_IRQ_AXIERRIRQ, \ 138 GIC_HIGHEST_SEC_PRIORITY, \ 139 grp, GIC_INTR_CFG_LEVEL), \ 140 INTR_PROP_DESC(STM32MP1_IRQ_TZC400, \ 141 GIC_HIGHEST_SEC_PRIORITY, \ 142 grp, GIC_INTR_CFG_LEVEL), \ 143 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \ 144 GIC_HIGHEST_SEC_PRIORITY, \ 145 grp, GIC_INTR_CFG_EDGE), \ 146 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \ 147 GIC_HIGHEST_SEC_PRIORITY, \ 148 grp, GIC_INTR_CFG_EDGE), \ 149 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \ 150 GIC_HIGHEST_SEC_PRIORITY, \ 151 grp, GIC_INTR_CFG_EDGE), \ 152 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \ 153 GIC_HIGHEST_SEC_PRIORITY, \ 154 grp, GIC_INTR_CFG_EDGE), \ 155 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \ 156 GIC_HIGHEST_SEC_PRIORITY, \ 157 grp, GIC_INTR_CFG_EDGE), \ 158 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \ 159 GIC_HIGHEST_SEC_PRIORITY, \ 160 grp, GIC_INTR_CFG_EDGE) 161 162 #define PLATFORM_G0_PROPS(grp) \ 163 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \ 164 GIC_HIGHEST_SEC_PRIORITY, \ 165 grp, GIC_INTR_CFG_EDGE), \ 166 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \ 167 GIC_HIGHEST_SEC_PRIORITY, \ 168 grp, GIC_INTR_CFG_EDGE) 169 170 /* 171 * Power 172 */ 173 #define PLAT_MAX_PWR_LVL U(1) 174 175 /* Local power state for power domains in Run state. */ 176 #define ARM_LOCAL_STATE_RUN U(0) 177 /* Local power state for retention. Valid only for CPU power domains */ 178 #define ARM_LOCAL_STATE_RET U(1) 179 /* Local power state for power-down. Valid for CPU and cluster power domains */ 180 #define ARM_LOCAL_STATE_OFF U(2) 181 /* 182 * This macro defines the deepest retention state possible. 183 * A higher state id will represent an invalid or a power down state. 184 */ 185 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 186 /* 187 * This macro defines the deepest power down states possible. Any state ID 188 * higher than this is invalid. 189 */ 190 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 191 192 /******************************************************************************* 193 * Size of the per-cpu data in bytes that should be reserved in the generic 194 * per-cpu data structure for the FVP port. 195 ******************************************************************************/ 196 #define PLAT_PCPU_DATA_SIZE 2 197 198 #endif /* PLATFORM_DEF_H */ 199