1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <drivers/arm/gic_common.h> 12 #include <lib/utils_def.h> 13 #include <plat/common/common_def.h> 14 15 #include "../stm32mp1_def.h" 16 17 /******************************************************************************* 18 * Generic platform constants 19 ******************************************************************************/ 20 21 /* Size of cacheable stacks */ 22 #if defined(IMAGE_BL32) 23 #define PLATFORM_STACK_SIZE 0x600 24 #else 25 #define PLATFORM_STACK_SIZE 0xC00 26 #endif 27 28 /* SSBL = second stage boot loader */ 29 #define BL33_IMAGE_NAME "ssbl" 30 #define BL33_BINARY_TYPE U(0x0) 31 32 #define STM32MP1_PRIMARY_CPU U(0x0) 33 34 #define PLATFORM_CACHE_LINE_SIZE 64 35 #define PLATFORM_CLUSTER_COUNT ULL(1) 36 #define PLATFORM_CLUSTER0_CORE_COUNT U(2) 37 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 38 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 39 PLATFORM_CLUSTER0_CORE_COUNT) 40 #define PLATFORM_MAX_CPUS_PER_CLUSTER 2 41 42 #define MAX_IO_DEVICES 4 43 #define MAX_IO_HANDLES 4 44 #define MAX_IO_BLOCK_DEVICES 1 45 46 /******************************************************************************* 47 * BL2 specific defines. 48 ******************************************************************************/ 49 /* 50 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 51 * size plus a little space for growth. 52 */ 53 #define BL2_BASE STM32MP1_BL2_BASE 54 #define BL2_LIMIT (STM32MP1_BL2_BASE + \ 55 STM32MP1_BL2_SIZE) 56 57 /******************************************************************************* 58 * BL32 specific defines. 59 ******************************************************************************/ 60 #define BL32_BASE STM32MP1_BL32_BASE 61 #define BL32_LIMIT (STM32MP1_BL32_BASE + \ 62 STM32MP1_BL32_SIZE) 63 64 /******************************************************************************* 65 * BL33 specific defines. 66 ******************************************************************************/ 67 #define BL33_BASE STM32MP1_BL33_BASE 68 69 /* 70 * Load address of BL33 for this platform port 71 */ 72 #define PLAT_STM32MP1_NS_IMAGE_OFFSET BL33_BASE 73 74 /******************************************************************************* 75 * DTB specific defines. 76 ******************************************************************************/ 77 #define DTB_BASE STM32MP1_DTB_BASE 78 #define DTB_LIMIT (STM32MP1_DTB_BASE + \ 79 STM32MP1_DTB_SIZE) 80 81 /******************************************************************************* 82 * Platform specific page table and MMU setup constants 83 ******************************************************************************/ 84 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 85 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 86 87 /******************************************************************************* 88 * Declarations and constants to access the mailboxes safely. Each mailbox is 89 * aligned on the biggest cache line size in the platform. This is known only 90 * to the platform as it might have a combination of integrated and external 91 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 92 * line at any cache level. They could belong to different cpus/clusters & 93 * get written while being protected by different locks causing corruption of 94 * a valid mailbox address. 95 ******************************************************************************/ 96 #define CACHE_WRITEBACK_SHIFT 6 97 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 98 99 /* 100 * Secure Interrupt: based on the standard ARM mapping 101 */ 102 #define ARM_IRQ_SEC_PHY_TIMER U(29) 103 104 #define ARM_IRQ_SEC_SGI_0 U(8) 105 #define ARM_IRQ_SEC_SGI_1 U(9) 106 #define ARM_IRQ_SEC_SGI_2 U(10) 107 #define ARM_IRQ_SEC_SGI_3 U(11) 108 #define ARM_IRQ_SEC_SGI_4 U(12) 109 #define ARM_IRQ_SEC_SGI_5 U(13) 110 #define ARM_IRQ_SEC_SGI_6 U(14) 111 #define ARM_IRQ_SEC_SGI_7 U(15) 112 113 #define STM32MP1_IRQ_TZC400 U(36) 114 #define STM32MP1_IRQ_TAMPSERRS U(229) 115 #define STM32MP1_IRQ_AXIERRIRQ U(244) 116 117 /* 118 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 119 * terminology. On a GICv2 system or mode, the lists will be merged and treated 120 * as Group 0 interrupts. 121 */ 122 #define PLATFORM_G1S_PROPS(grp) \ 123 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \ 124 GIC_HIGHEST_SEC_PRIORITY, \ 125 grp, GIC_INTR_CFG_LEVEL), \ 126 INTR_PROP_DESC(STM32MP1_IRQ_TAMPSERRS, \ 127 GIC_HIGHEST_SEC_PRIORITY, \ 128 grp, GIC_INTR_CFG_LEVEL), \ 129 INTR_PROP_DESC(STM32MP1_IRQ_AXIERRIRQ, \ 130 GIC_HIGHEST_SEC_PRIORITY, \ 131 grp, GIC_INTR_CFG_LEVEL), \ 132 INTR_PROP_DESC(STM32MP1_IRQ_TZC400, \ 133 GIC_HIGHEST_SEC_PRIORITY, \ 134 grp, GIC_INTR_CFG_LEVEL), \ 135 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \ 136 GIC_HIGHEST_SEC_PRIORITY, \ 137 grp, GIC_INTR_CFG_EDGE), \ 138 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \ 139 GIC_HIGHEST_SEC_PRIORITY, \ 140 grp, GIC_INTR_CFG_EDGE), \ 141 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \ 142 GIC_HIGHEST_SEC_PRIORITY, \ 143 grp, GIC_INTR_CFG_EDGE), \ 144 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \ 145 GIC_HIGHEST_SEC_PRIORITY, \ 146 grp, GIC_INTR_CFG_EDGE), \ 147 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \ 148 GIC_HIGHEST_SEC_PRIORITY, \ 149 grp, GIC_INTR_CFG_EDGE), \ 150 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \ 151 GIC_HIGHEST_SEC_PRIORITY, \ 152 grp, GIC_INTR_CFG_EDGE) 153 154 #define PLATFORM_G0_PROPS(grp) \ 155 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \ 156 GIC_HIGHEST_SEC_PRIORITY, \ 157 grp, GIC_INTR_CFG_EDGE), \ 158 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \ 159 GIC_HIGHEST_SEC_PRIORITY, \ 160 grp, GIC_INTR_CFG_EDGE) 161 162 /* 163 * Power 164 */ 165 #define PLAT_MAX_PWR_LVL U(1) 166 167 /* Local power state for power domains in Run state. */ 168 #define ARM_LOCAL_STATE_RUN U(0) 169 /* Local power state for retention. Valid only for CPU power domains */ 170 #define ARM_LOCAL_STATE_RET U(1) 171 /* Local power state for power-down. Valid for CPU and cluster power domains */ 172 #define ARM_LOCAL_STATE_OFF U(2) 173 /* 174 * This macro defines the deepest retention state possible. 175 * A higher state id will represent an invalid or a power down state. 176 */ 177 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 178 /* 179 * This macro defines the deepest power down states possible. Any state ID 180 * higher than this is invalid. 181 */ 182 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 183 184 /******************************************************************************* 185 * Size of the per-cpu data in bytes that should be reserved in the generic 186 * per-cpu data structure for the FVP port. 187 ******************************************************************************/ 188 #define PLAT_PCPU_DATA_SIZE 2 189 190 #endif /* PLATFORM_DEF_H */ 191