1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <drivers/arm/gic_common.h> 12 #include <lib/utils_def.h> 13 #include <plat/common/common_def.h> 14 15 #include "../stm32mp1_def.h" 16 17 /******************************************************************************* 18 * Generic platform constants 19 ******************************************************************************/ 20 21 /* Size of cacheable stacks */ 22 #if defined(IMAGE_BL32) 23 #define PLATFORM_STACK_SIZE 0x600 24 #else 25 #define PLATFORM_STACK_SIZE 0xC00 26 #endif 27 28 #if STM32MP_USE_STM32IMAGE 29 #ifdef AARCH32_SP_OPTEE 30 #define OPTEE_HEADER_IMAGE_NAME "teeh" 31 #define OPTEE_CORE_IMAGE_NAME "teex" 32 #define OPTEE_PAGED_IMAGE_NAME "teed" 33 #define OPTEE_HEADER_BINARY_TYPE U(0x20) 34 #define OPTEE_CORE_BINARY_TYPE U(0x21) 35 #define OPTEE_PAGED_BINARY_TYPE U(0x22) 36 #endif 37 38 /* SSBL = second stage boot loader */ 39 #define BL33_IMAGE_NAME "ssbl" 40 #define BL33_BINARY_TYPE U(0x0) 41 #else /* STM32MP_USE_STM32IMAGE */ 42 #define FIP_IMAGE_NAME "fip" 43 #define METADATA_PART_1 "metadata1" 44 #define METADATA_PART_2 "metadata2" 45 46 #endif /* STM32MP_USE_STM32IMAGE */ 47 48 #define STM32MP_PRIMARY_CPU U(0x0) 49 #define STM32MP_SECONDARY_CPU U(0x1) 50 51 #define PLATFORM_CLUSTER_COUNT U(1) 52 #define PLATFORM_CLUSTER0_CORE_COUNT U(2) 53 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 54 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 55 PLATFORM_CLUSTER0_CORE_COUNT) 56 #define PLATFORM_MAX_CPUS_PER_CLUSTER 2 57 58 #define MAX_IO_DEVICES U(4) 59 #define MAX_IO_HANDLES U(4) 60 #define MAX_IO_BLOCK_DEVICES U(1) 61 #define MAX_IO_MTD_DEVICES U(1) 62 63 /******************************************************************************* 64 * BL2 specific defines. 65 ******************************************************************************/ 66 /* 67 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 68 * size plus a little space for growth. 69 */ 70 #define BL2_BASE STM32MP_BL2_BASE 71 #define BL2_LIMIT (STM32MP_BL2_BASE + \ 72 STM32MP_BL2_SIZE) 73 74 #define BL2_RO_BASE STM32MP_BL2_RO_BASE 75 #define BL2_RO_LIMIT (STM32MP_BL2_RO_BASE + \ 76 STM32MP_BL2_RO_SIZE) 77 78 #define BL2_RW_BASE STM32MP_BL2_RW_BASE 79 #define BL2_RW_LIMIT (STM32MP_BL2_RW_BASE + \ 80 STM32MP_BL2_RW_SIZE) 81 /******************************************************************************* 82 * BL32 specific defines. 83 ******************************************************************************/ 84 #if STM32MP_USE_STM32IMAGE || defined(IMAGE_BL32) 85 #if ENABLE_PIE 86 #define BL32_BASE 0 87 #define BL32_LIMIT STM32MP_BL32_SIZE 88 #else 89 #define BL32_BASE STM32MP_BL32_BASE 90 #define BL32_LIMIT (STM32MP_BL32_BASE + \ 91 STM32MP_BL32_SIZE) 92 #endif 93 #endif /* STM32MP_USE_STM32IMAGE || defined(IMAGE_BL32) */ 94 95 /******************************************************************************* 96 * BL33 specific defines. 97 ******************************************************************************/ 98 #define BL33_BASE STM32MP_BL33_BASE 99 100 /* 101 * Load address of BL33 for this platform port 102 */ 103 #define PLAT_STM32MP_NS_IMAGE_OFFSET BL33_BASE 104 105 /* Needed by STM32CubeProgrammer support */ 106 #define DWL_BUFFER_SIZE U(0x01000000) 107 108 /* 109 * SSBL offset in case it's stored in eMMC boot partition. 110 * We can fix it to 256K because TF-A size can't be bigger than SRAM 111 */ 112 #define PLAT_EMMC_BOOT_SSBL_OFFSET U(0x40000) 113 114 /******************************************************************************* 115 * DTB specific defines. 116 ******************************************************************************/ 117 #define DTB_BASE STM32MP_DTB_BASE 118 #define DTB_LIMIT (STM32MP_DTB_BASE + \ 119 STM32MP_DTB_SIZE) 120 121 /******************************************************************************* 122 * Platform specific page table and MMU setup constants 123 ******************************************************************************/ 124 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) 125 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) 126 127 /******************************************************************************* 128 * Declarations and constants to access the mailboxes safely. Each mailbox is 129 * aligned on the biggest cache line size in the platform. This is known only 130 * to the platform as it might have a combination of integrated and external 131 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 132 * line at any cache level. They could belong to different cpus/clusters & 133 * get written while being protected by different locks causing corruption of 134 * a valid mailbox address. 135 ******************************************************************************/ 136 #define CACHE_WRITEBACK_SHIFT 6 137 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 138 139 /* 140 * Secure Interrupt: based on the standard ARM mapping 141 */ 142 #define ARM_IRQ_SEC_PHY_TIMER U(29) 143 144 #define ARM_IRQ_SEC_SGI_0 U(8) 145 #define ARM_IRQ_SEC_SGI_1 U(9) 146 #define ARM_IRQ_SEC_SGI_2 U(10) 147 #define ARM_IRQ_SEC_SGI_3 U(11) 148 #define ARM_IRQ_SEC_SGI_4 U(12) 149 #define ARM_IRQ_SEC_SGI_5 U(13) 150 #define ARM_IRQ_SEC_SGI_6 U(14) 151 #define ARM_IRQ_SEC_SGI_7 U(15) 152 153 #define STM32MP1_IRQ_TZC400 U(36) 154 #define STM32MP1_IRQ_TAMPSERRS U(229) 155 #define STM32MP1_IRQ_AXIERRIRQ U(244) 156 157 /* 158 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 159 * terminology. On a GICv2 system or mode, the lists will be merged and treated 160 * as Group 0 interrupts. 161 */ 162 #define PLATFORM_G1S_PROPS(grp) \ 163 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \ 164 GIC_HIGHEST_SEC_PRIORITY, \ 165 grp, GIC_INTR_CFG_LEVEL), \ 166 INTR_PROP_DESC(STM32MP1_IRQ_AXIERRIRQ, \ 167 GIC_HIGHEST_SEC_PRIORITY, \ 168 grp, GIC_INTR_CFG_LEVEL), \ 169 INTR_PROP_DESC(STM32MP1_IRQ_TZC400, \ 170 GIC_HIGHEST_SEC_PRIORITY, \ 171 grp, GIC_INTR_CFG_LEVEL), \ 172 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \ 173 GIC_HIGHEST_SEC_PRIORITY, \ 174 grp, GIC_INTR_CFG_EDGE), \ 175 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \ 176 GIC_HIGHEST_SEC_PRIORITY, \ 177 grp, GIC_INTR_CFG_EDGE), \ 178 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \ 179 GIC_HIGHEST_SEC_PRIORITY, \ 180 grp, GIC_INTR_CFG_EDGE), \ 181 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \ 182 GIC_HIGHEST_SEC_PRIORITY, \ 183 grp, GIC_INTR_CFG_EDGE), \ 184 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \ 185 GIC_HIGHEST_SEC_PRIORITY, \ 186 grp, GIC_INTR_CFG_EDGE), \ 187 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \ 188 GIC_HIGHEST_SEC_PRIORITY, \ 189 grp, GIC_INTR_CFG_EDGE) 190 191 #define PLATFORM_G0_PROPS(grp) \ 192 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \ 193 GIC_HIGHEST_SEC_PRIORITY, \ 194 grp, GIC_INTR_CFG_EDGE), \ 195 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \ 196 GIC_HIGHEST_SEC_PRIORITY, \ 197 grp, GIC_INTR_CFG_EDGE) 198 199 /* 200 * Power 201 */ 202 #define PLAT_MAX_PWR_LVL U(1) 203 204 /* Local power state for power domains in Run state. */ 205 #define ARM_LOCAL_STATE_RUN U(0) 206 /* Local power state for retention. Valid only for CPU power domains */ 207 #define ARM_LOCAL_STATE_RET U(1) 208 /* Local power state for power-down. Valid for CPU and cluster power domains */ 209 #define ARM_LOCAL_STATE_OFF U(2) 210 /* 211 * This macro defines the deepest retention state possible. 212 * A higher state id will represent an invalid or a power down state. 213 */ 214 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 215 /* 216 * This macro defines the deepest power down states possible. Any state ID 217 * higher than this is invalid. 218 */ 219 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 220 221 /******************************************************************************* 222 * Size of the per-cpu data in bytes that should be reserved in the generic 223 * per-cpu data structure for the FVP port. 224 ******************************************************************************/ 225 #define PLAT_PCPU_DATA_SIZE 2 226 227 /******************************************************************************* 228 * Number of parallel entry slots in SMT SCMI server entry context. For this 229 * platform, SCMI server is reached through SMC only, hence the number of 230 * entry slots. 231 ******************************************************************************/ 232 #define PLAT_SMT_ENTRY_COUNT PLATFORM_CORE_COUNT 233 234 #endif /* PLATFORM_DEF_H */ 235