1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <common_def.h> 12 #include <gic_common.h> 13 #include <utils_def.h> 14 #include "../stm32mp1_def.h" 15 16 /******************************************************************************* 17 * Generic platform constants 18 ******************************************************************************/ 19 20 /* Size of cacheable stacks */ 21 #if defined(IMAGE_BL32) 22 #define PLATFORM_STACK_SIZE 0x600 23 #else 24 #define PLATFORM_STACK_SIZE 0xC00 25 #endif 26 27 /* SSBL = second stage boot loader */ 28 #define BL33_IMAGE_NAME "ssbl" 29 30 #define STM32MP1_PRIMARY_CPU U(0x0) 31 32 #define PLATFORM_CACHE_LINE_SIZE 64 33 #define PLATFORM_CLUSTER_COUNT ULL(1) 34 #define PLATFORM_CLUSTER0_CORE_COUNT U(2) 35 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 36 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 37 PLATFORM_CLUSTER0_CORE_COUNT) 38 #define PLATFORM_MAX_CPUS_PER_CLUSTER 2 39 40 #define MAX_IO_DEVICES 4 41 #define MAX_IO_HANDLES 4 42 43 /******************************************************************************* 44 * BL2 specific defines. 45 ******************************************************************************/ 46 /* 47 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 48 * size plus a little space for growth. 49 */ 50 #define BL2_BASE STM32MP1_BL2_BASE 51 #define BL2_LIMIT (STM32MP1_BL2_BASE + \ 52 STM32MP1_BL2_SIZE) 53 54 /******************************************************************************* 55 * BL32 specific defines. 56 ******************************************************************************/ 57 #define BL32_BASE STM32MP1_BL32_BASE 58 #define BL32_LIMIT (STM32MP1_BL32_BASE + \ 59 STM32MP1_BL32_SIZE) 60 61 /******************************************************************************* 62 * BL33 specific defines. 63 ******************************************************************************/ 64 #define BL33_BASE STM32MP1_BL33_BASE 65 66 /* 67 * Load address of BL33 for this platform port 68 */ 69 #define PLAT_STM32MP1_NS_IMAGE_OFFSET BL33_BASE 70 71 /******************************************************************************* 72 * DTB specific defines. 73 ******************************************************************************/ 74 #define DTB_BASE STM32MP1_DTB_BASE 75 #define DTB_LIMIT (STM32MP1_DTB_BASE + \ 76 STM32MP1_DTB_SIZE) 77 78 /******************************************************************************* 79 * Platform specific page table and MMU setup constants 80 ******************************************************************************/ 81 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 82 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 83 84 /******************************************************************************* 85 * Declarations and constants to access the mailboxes safely. Each mailbox is 86 * aligned on the biggest cache line size in the platform. This is known only 87 * to the platform as it might have a combination of integrated and external 88 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 89 * line at any cache level. They could belong to different cpus/clusters & 90 * get written while being protected by different locks causing corruption of 91 * a valid mailbox address. 92 ******************************************************************************/ 93 #define CACHE_WRITEBACK_SHIFT 6 94 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 95 96 /* 97 * Secure Interrupt: based on the standard ARM mapping 98 */ 99 #define ARM_IRQ_SEC_PHY_TIMER U(29) 100 101 #define ARM_IRQ_SEC_SGI_0 U(8) 102 #define ARM_IRQ_SEC_SGI_1 U(9) 103 #define ARM_IRQ_SEC_SGI_2 U(10) 104 #define ARM_IRQ_SEC_SGI_3 U(11) 105 #define ARM_IRQ_SEC_SGI_4 U(12) 106 #define ARM_IRQ_SEC_SGI_5 U(13) 107 #define ARM_IRQ_SEC_SGI_6 U(14) 108 #define ARM_IRQ_SEC_SGI_7 U(15) 109 110 #define STM32MP1_IRQ_TZC400 U(36) 111 #define STM32MP1_IRQ_TAMPSERRS U(229) 112 #define STM32MP1_IRQ_AXIERRIRQ U(244) 113 114 /* 115 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 116 * terminology. On a GICv2 system or mode, the lists will be merged and treated 117 * as Group 0 interrupts. 118 */ 119 #define PLATFORM_G1S_PROPS(grp) \ 120 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \ 121 GIC_HIGHEST_SEC_PRIORITY, \ 122 grp, GIC_INTR_CFG_LEVEL), \ 123 INTR_PROP_DESC(STM32MP1_IRQ_TAMPSERRS, \ 124 GIC_HIGHEST_SEC_PRIORITY, \ 125 grp, GIC_INTR_CFG_LEVEL), \ 126 INTR_PROP_DESC(STM32MP1_IRQ_AXIERRIRQ, \ 127 GIC_HIGHEST_SEC_PRIORITY, \ 128 grp, GIC_INTR_CFG_LEVEL), \ 129 INTR_PROP_DESC(STM32MP1_IRQ_TZC400, \ 130 GIC_HIGHEST_SEC_PRIORITY, \ 131 grp, GIC_INTR_CFG_LEVEL), \ 132 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \ 133 GIC_HIGHEST_SEC_PRIORITY, \ 134 grp, GIC_INTR_CFG_EDGE), \ 135 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \ 136 GIC_HIGHEST_SEC_PRIORITY, \ 137 grp, GIC_INTR_CFG_EDGE), \ 138 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \ 139 GIC_HIGHEST_SEC_PRIORITY, \ 140 grp, GIC_INTR_CFG_EDGE), \ 141 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \ 142 GIC_HIGHEST_SEC_PRIORITY, \ 143 grp, GIC_INTR_CFG_EDGE), \ 144 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \ 145 GIC_HIGHEST_SEC_PRIORITY, \ 146 grp, GIC_INTR_CFG_EDGE), \ 147 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \ 148 GIC_HIGHEST_SEC_PRIORITY, \ 149 grp, GIC_INTR_CFG_EDGE) 150 151 #define PLATFORM_G0_PROPS(grp) \ 152 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \ 153 GIC_HIGHEST_SEC_PRIORITY, \ 154 grp, GIC_INTR_CFG_EDGE), \ 155 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \ 156 GIC_HIGHEST_SEC_PRIORITY, \ 157 grp, GIC_INTR_CFG_EDGE) 158 159 /* 160 * Power 161 */ 162 #define PLAT_MAX_PWR_LVL U(1) 163 164 /* Local power state for power domains in Run state. */ 165 #define ARM_LOCAL_STATE_RUN U(0) 166 /* Local power state for retention. Valid only for CPU power domains */ 167 #define ARM_LOCAL_STATE_RET U(1) 168 /* Local power state for power-down. Valid for CPU and cluster power domains */ 169 #define ARM_LOCAL_STATE_OFF U(2) 170 /* 171 * This macro defines the deepest retention state possible. 172 * A higher state id will represent an invalid or a power down state. 173 */ 174 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 175 /* 176 * This macro defines the deepest power down states possible. Any state ID 177 * higher than this is invalid. 178 */ 179 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 180 181 /******************************************************************************* 182 * Size of the per-cpu data in bytes that should be reserved in the generic 183 * per-cpu data structure for the FVP port. 184 ******************************************************************************/ 185 #define PLAT_PCPU_DATA_SIZE 2 186 187 #endif /* PLATFORM_DEF_H */ 188