1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/desc_image_load.h> 16 #include <drivers/delay_timer.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/st/stm32_console.h> 19 #include <drivers/st/stm32mp_pmic.h> 20 #include <drivers/st/stm32mp_reset.h> 21 #include <drivers/st/stm32mp1_clk.h> 22 #include <drivers/st/stm32mp1_pwr.h> 23 #include <drivers/st/stm32mp1_ram.h> 24 #include <lib/mmio.h> 25 #include <lib/optee_utils.h> 26 #include <lib/xlat_tables/xlat_tables_v2.h> 27 #include <plat/common/platform.h> 28 29 #include <stm32mp1_context.h> 30 31 static struct console_stm32 console; 32 33 static void print_reset_reason(void) 34 { 35 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR); 36 37 if (rstsr == 0U) { 38 WARN("Reset reason unknown\n"); 39 return; 40 } 41 42 INFO("Reset reason (0x%x):\n", rstsr); 43 44 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) { 45 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) { 46 INFO("System exits from STANDBY\n"); 47 return; 48 } 49 50 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) { 51 INFO("MPU exits from CSTANDBY\n"); 52 return; 53 } 54 } 55 56 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) { 57 INFO(" Power-on Reset (rst_por)\n"); 58 return; 59 } 60 61 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) { 62 INFO(" Brownout Reset (rst_bor)\n"); 63 return; 64 } 65 66 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) { 67 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 68 INFO(" System reset generated by MCU (MCSYSRST)\n"); 69 } else { 70 INFO(" Local reset generated by MCU (MCSYSRST)\n"); 71 } 72 return; 73 } 74 75 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) { 76 INFO(" System reset generated by MPU (MPSYSRST)\n"); 77 return; 78 } 79 80 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) { 81 INFO(" Reset due to a clock failure on HSE\n"); 82 return; 83 } 84 85 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) { 86 INFO(" IWDG1 Reset (rst_iwdg1)\n"); 87 return; 88 } 89 90 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) { 91 INFO(" IWDG2 Reset (rst_iwdg2)\n"); 92 return; 93 } 94 95 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) { 96 INFO(" MPU Processor 0 Reset\n"); 97 return; 98 } 99 100 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) { 101 INFO(" MPU Processor 1 Reset\n"); 102 return; 103 } 104 105 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 106 INFO(" Pad Reset from NRST\n"); 107 return; 108 } 109 110 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) { 111 INFO(" Reset due to a failure of VDD_CORE\n"); 112 return; 113 } 114 115 ERROR(" Unidentified reset reason\n"); 116 } 117 118 void bl2_el3_early_platform_setup(u_register_t arg0, 119 u_register_t arg1 __unused, 120 u_register_t arg2 __unused, 121 u_register_t arg3 __unused) 122 { 123 stm32mp_save_boot_ctx_address(arg0); 124 } 125 126 void bl2_platform_setup(void) 127 { 128 int ret; 129 130 if (dt_pmic_status() > 0) { 131 initialize_pmic(); 132 } 133 134 ret = stm32mp1_ddr_probe(); 135 if (ret < 0) { 136 ERROR("Invalid DDR init: error %d\n", ret); 137 panic(); 138 } 139 140 #ifdef AARCH32_SP_OPTEE 141 INFO("BL2 runs OP-TEE setup\n"); 142 /* Initialize tzc400 after DDR initialization */ 143 stm32mp1_security_setup(); 144 #else 145 INFO("BL2 runs SP_MIN setup\n"); 146 #endif 147 } 148 149 void bl2_el3_plat_arch_setup(void) 150 { 151 int32_t result; 152 struct dt_node_info dt_uart_info; 153 const char *board_model; 154 boot_api_context_t *boot_context = 155 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 156 uint32_t clk_rate; 157 uintptr_t pwr_base; 158 uintptr_t rcc_base; 159 160 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 161 BL_CODE_END - BL_CODE_BASE, 162 MT_CODE | MT_SECURE); 163 164 #ifdef AARCH32_SP_OPTEE 165 /* OP-TEE image needs post load processing: keep RAM read/write */ 166 mmap_add_region(STM32MP_DDR_BASE + dt_get_ddr_size() - 167 STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE, 168 STM32MP_DDR_BASE + dt_get_ddr_size() - 169 STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE, 170 STM32MP_DDR_S_SIZE, 171 MT_MEMORY | MT_RW | MT_SECURE); 172 173 mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE, 174 STM32MP_OPTEE_SIZE, 175 MT_MEMORY | MT_RW | MT_SECURE); 176 #else 177 /* Prevent corruption of preloaded BL32 */ 178 mmap_add_region(BL32_BASE, BL32_BASE, 179 BL32_LIMIT - BL32_BASE, 180 MT_MEMORY | MT_RO | MT_SECURE); 181 182 #endif 183 /* Map non secure DDR for BL33 load and DDR training area restore */ 184 mmap_add_region(STM32MP_DDR_BASE, 185 STM32MP_DDR_BASE, 186 STM32MP_DDR_MAX_SIZE, 187 MT_MEMORY | MT_RW | MT_NS); 188 189 /* Prevent corruption of preloaded Device Tree */ 190 mmap_add_region(DTB_BASE, DTB_BASE, 191 DTB_LIMIT - DTB_BASE, 192 MT_MEMORY | MT_RO | MT_SECURE); 193 194 configure_mmu(); 195 196 if (dt_open_and_check() < 0) { 197 panic(); 198 } 199 200 pwr_base = stm32mp_pwr_base(); 201 rcc_base = stm32mp_rcc_base(); 202 203 /* 204 * Disable the backup domain write protection. 205 * The protection is enable at each reset by hardware 206 * and must be disabled by software. 207 */ 208 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP); 209 210 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) { 211 ; 212 } 213 214 /* Reset backup domain on cold boot cases */ 215 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 216 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 217 218 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 219 0U) { 220 ; 221 } 222 223 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 224 } 225 226 /* Disable MCKPROT */ 227 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); 228 229 generic_delay_timer_init(); 230 231 if (stm32mp1_clk_probe() < 0) { 232 panic(); 233 } 234 235 if (stm32mp1_clk_init() < 0) { 236 panic(); 237 } 238 239 result = dt_get_stdout_uart_info(&dt_uart_info); 240 241 if ((result <= 0) || 242 (dt_uart_info.status == 0U) || 243 (dt_uart_info.clock < 0) || 244 (dt_uart_info.reset < 0)) { 245 goto skip_console_init; 246 } 247 248 if (dt_set_stdout_pinctrl() != 0) { 249 goto skip_console_init; 250 } 251 252 stm32mp_clk_enable((unsigned long)dt_uart_info.clock); 253 254 stm32mp_reset_assert((uint32_t)dt_uart_info.reset); 255 udelay(2); 256 stm32mp_reset_deassert((uint32_t)dt_uart_info.reset); 257 mdelay(1); 258 259 clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock); 260 261 if (console_stm32_register(dt_uart_info.base, clk_rate, 262 STM32MP_UART_BAUDRATE, &console) == 0) { 263 panic(); 264 } 265 266 board_model = dt_get_board_model(); 267 if (board_model != NULL) { 268 NOTICE("Model: %s\n", board_model); 269 } 270 271 skip_console_init: 272 273 if (stm32_save_boot_interface(boot_context->boot_interface_selected, 274 boot_context->boot_interface_instance) != 275 0) { 276 ERROR("Cannot save boot interface\n"); 277 } 278 279 stm32mp1_arch_security_setup(); 280 281 print_reset_reason(); 282 283 stm32mp_io_setup(); 284 } 285 286 #if defined(AARCH32_SP_OPTEE) 287 /******************************************************************************* 288 * This function can be used by the platforms to update/use image 289 * information for given `image_id`. 290 ******************************************************************************/ 291 int bl2_plat_handle_post_image_load(unsigned int image_id) 292 { 293 int err = 0; 294 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 295 bl_mem_params_node_t *bl32_mem_params; 296 bl_mem_params_node_t *pager_mem_params; 297 bl_mem_params_node_t *paged_mem_params; 298 299 assert(bl_mem_params != NULL); 300 301 switch (image_id) { 302 case BL32_IMAGE_ID: 303 bl_mem_params->ep_info.pc = 304 bl_mem_params->image_info.image_base; 305 306 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 307 assert(pager_mem_params != NULL); 308 pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE; 309 pager_mem_params->image_info.image_max_size = 310 STM32MP_OPTEE_SIZE; 311 312 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 313 assert(paged_mem_params != NULL); 314 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 315 (dt_get_ddr_size() - STM32MP_DDR_S_SIZE - 316 STM32MP_DDR_SHMEM_SIZE); 317 paged_mem_params->image_info.image_max_size = 318 STM32MP_DDR_S_SIZE; 319 320 err = parse_optee_header(&bl_mem_params->ep_info, 321 &pager_mem_params->image_info, 322 &paged_mem_params->image_info); 323 if (err) { 324 ERROR("OPTEE header parse error.\n"); 325 panic(); 326 } 327 328 /* Set optee boot info from parsed header data */ 329 bl_mem_params->ep_info.pc = 330 pager_mem_params->image_info.image_base; 331 bl_mem_params->ep_info.args.arg0 = 332 paged_mem_params->image_info.image_base; 333 bl_mem_params->ep_info.args.arg1 = 0; /* Unused */ 334 bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */ 335 break; 336 337 case BL33_IMAGE_ID: 338 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); 339 assert(bl32_mem_params != NULL); 340 bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; 341 break; 342 343 default: 344 /* Do nothing in default case */ 345 break; 346 } 347 348 return err; 349 } 350 #endif 351