1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/desc_image_load.h> 16 #include <drivers/delay_timer.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/st/bsec.h> 19 #include <drivers/st/stm32_console.h> 20 #include <drivers/st/stm32mp_pmic.h> 21 #include <drivers/st/stm32mp_reset.h> 22 #include <drivers/st/stm32mp1_clk.h> 23 #include <drivers/st/stm32mp1_pwr.h> 24 #include <drivers/st/stm32mp1_ram.h> 25 #include <lib/mmio.h> 26 #include <lib/optee_utils.h> 27 #include <lib/xlat_tables/xlat_tables_v2.h> 28 #include <plat/common/platform.h> 29 30 #include <stm32mp1_context.h> 31 32 static struct console_stm32 console; 33 34 static void print_reset_reason(void) 35 { 36 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR); 37 38 if (rstsr == 0U) { 39 WARN("Reset reason unknown\n"); 40 return; 41 } 42 43 INFO("Reset reason (0x%x):\n", rstsr); 44 45 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) { 46 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) { 47 INFO("System exits from STANDBY\n"); 48 return; 49 } 50 51 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) { 52 INFO("MPU exits from CSTANDBY\n"); 53 return; 54 } 55 } 56 57 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) { 58 INFO(" Power-on Reset (rst_por)\n"); 59 return; 60 } 61 62 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) { 63 INFO(" Brownout Reset (rst_bor)\n"); 64 return; 65 } 66 67 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) { 68 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 69 INFO(" System reset generated by MCU (MCSYSRST)\n"); 70 } else { 71 INFO(" Local reset generated by MCU (MCSYSRST)\n"); 72 } 73 return; 74 } 75 76 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) { 77 INFO(" System reset generated by MPU (MPSYSRST)\n"); 78 return; 79 } 80 81 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) { 82 INFO(" Reset due to a clock failure on HSE\n"); 83 return; 84 } 85 86 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) { 87 INFO(" IWDG1 Reset (rst_iwdg1)\n"); 88 return; 89 } 90 91 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) { 92 INFO(" IWDG2 Reset (rst_iwdg2)\n"); 93 return; 94 } 95 96 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) { 97 INFO(" MPU Processor 0 Reset\n"); 98 return; 99 } 100 101 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) { 102 INFO(" MPU Processor 1 Reset\n"); 103 return; 104 } 105 106 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 107 INFO(" Pad Reset from NRST\n"); 108 return; 109 } 110 111 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) { 112 INFO(" Reset due to a failure of VDD_CORE\n"); 113 return; 114 } 115 116 ERROR(" Unidentified reset reason\n"); 117 } 118 119 void bl2_el3_early_platform_setup(u_register_t arg0, 120 u_register_t arg1 __unused, 121 u_register_t arg2 __unused, 122 u_register_t arg3 __unused) 123 { 124 stm32mp_save_boot_ctx_address(arg0); 125 } 126 127 void bl2_platform_setup(void) 128 { 129 int ret; 130 131 if (dt_pmic_status() > 0) { 132 initialize_pmic(); 133 } 134 135 ret = stm32mp1_ddr_probe(); 136 if (ret < 0) { 137 ERROR("Invalid DDR init: error %d\n", ret); 138 panic(); 139 } 140 141 #ifdef AARCH32_SP_OPTEE 142 INFO("BL2 runs OP-TEE setup\n"); 143 /* Initialize tzc400 after DDR initialization */ 144 stm32mp1_security_setup(); 145 #else 146 INFO("BL2 runs SP_MIN setup\n"); 147 #endif 148 } 149 150 void bl2_el3_plat_arch_setup(void) 151 { 152 int32_t result; 153 struct dt_node_info dt_uart_info; 154 const char *board_model; 155 boot_api_context_t *boot_context = 156 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 157 uint32_t clk_rate; 158 uintptr_t pwr_base; 159 uintptr_t rcc_base; 160 161 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 162 BL_CODE_END - BL_CODE_BASE, 163 MT_CODE | MT_SECURE); 164 165 #ifdef AARCH32_SP_OPTEE 166 /* OP-TEE image needs post load processing: keep RAM read/write */ 167 mmap_add_region(STM32MP_DDR_BASE + dt_get_ddr_size() - 168 STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE, 169 STM32MP_DDR_BASE + dt_get_ddr_size() - 170 STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE, 171 STM32MP_DDR_S_SIZE, 172 MT_MEMORY | MT_RW | MT_SECURE); 173 174 mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE, 175 STM32MP_OPTEE_SIZE, 176 MT_MEMORY | MT_RW | MT_SECURE); 177 #else 178 /* Prevent corruption of preloaded BL32 */ 179 mmap_add_region(BL32_BASE, BL32_BASE, 180 BL32_LIMIT - BL32_BASE, 181 MT_MEMORY | MT_RO | MT_SECURE); 182 183 #endif 184 /* Map non secure DDR for BL33 load and DDR training area restore */ 185 mmap_add_region(STM32MP_DDR_BASE, 186 STM32MP_DDR_BASE, 187 STM32MP_DDR_MAX_SIZE, 188 MT_MEMORY | MT_RW | MT_NS); 189 190 /* Prevent corruption of preloaded Device Tree */ 191 mmap_add_region(DTB_BASE, DTB_BASE, 192 DTB_LIMIT - DTB_BASE, 193 MT_MEMORY | MT_RO | MT_SECURE); 194 195 configure_mmu(); 196 197 if (dt_open_and_check() < 0) { 198 panic(); 199 } 200 201 pwr_base = stm32mp_pwr_base(); 202 rcc_base = stm32mp_rcc_base(); 203 204 /* 205 * Disable the backup domain write protection. 206 * The protection is enable at each reset by hardware 207 * and must be disabled by software. 208 */ 209 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP); 210 211 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) { 212 ; 213 } 214 215 if (bsec_probe() != 0) { 216 panic(); 217 } 218 219 /* Reset backup domain on cold boot cases */ 220 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 221 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 222 223 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 224 0U) { 225 ; 226 } 227 228 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 229 } 230 231 /* Disable MCKPROT */ 232 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); 233 234 generic_delay_timer_init(); 235 236 if (stm32mp1_clk_probe() < 0) { 237 panic(); 238 } 239 240 if (stm32mp1_clk_init() < 0) { 241 panic(); 242 } 243 244 stm32mp1_syscfg_init(); 245 246 result = dt_get_stdout_uart_info(&dt_uart_info); 247 248 if ((result <= 0) || 249 (dt_uart_info.status == 0U) || 250 (dt_uart_info.clock < 0) || 251 (dt_uart_info.reset < 0)) { 252 goto skip_console_init; 253 } 254 255 if (dt_set_stdout_pinctrl() != 0) { 256 goto skip_console_init; 257 } 258 259 stm32mp_clk_enable((unsigned long)dt_uart_info.clock); 260 261 stm32mp_reset_assert((uint32_t)dt_uart_info.reset); 262 udelay(2); 263 stm32mp_reset_deassert((uint32_t)dt_uart_info.reset); 264 mdelay(1); 265 266 clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock); 267 268 if (console_stm32_register(dt_uart_info.base, clk_rate, 269 STM32MP_UART_BAUDRATE, &console) == 0) { 270 panic(); 271 } 272 273 board_model = dt_get_board_model(); 274 if (board_model != NULL) { 275 NOTICE("Model: %s\n", board_model); 276 } 277 278 skip_console_init: 279 280 if (stm32_save_boot_interface(boot_context->boot_interface_selected, 281 boot_context->boot_interface_instance) != 282 0) { 283 ERROR("Cannot save boot interface\n"); 284 } 285 286 stm32mp1_arch_security_setup(); 287 288 print_reset_reason(); 289 290 stm32mp_io_setup(); 291 } 292 293 #if defined(AARCH32_SP_OPTEE) 294 /******************************************************************************* 295 * This function can be used by the platforms to update/use image 296 * information for given `image_id`. 297 ******************************************************************************/ 298 int bl2_plat_handle_post_image_load(unsigned int image_id) 299 { 300 int err = 0; 301 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 302 bl_mem_params_node_t *bl32_mem_params; 303 bl_mem_params_node_t *pager_mem_params; 304 bl_mem_params_node_t *paged_mem_params; 305 306 assert(bl_mem_params != NULL); 307 308 switch (image_id) { 309 case BL32_IMAGE_ID: 310 bl_mem_params->ep_info.pc = 311 bl_mem_params->image_info.image_base; 312 313 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 314 assert(pager_mem_params != NULL); 315 pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE; 316 pager_mem_params->image_info.image_max_size = 317 STM32MP_OPTEE_SIZE; 318 319 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 320 assert(paged_mem_params != NULL); 321 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 322 (dt_get_ddr_size() - STM32MP_DDR_S_SIZE - 323 STM32MP_DDR_SHMEM_SIZE); 324 paged_mem_params->image_info.image_max_size = 325 STM32MP_DDR_S_SIZE; 326 327 err = parse_optee_header(&bl_mem_params->ep_info, 328 &pager_mem_params->image_info, 329 &paged_mem_params->image_info); 330 if (err) { 331 ERROR("OPTEE header parse error.\n"); 332 panic(); 333 } 334 335 /* Set optee boot info from parsed header data */ 336 bl_mem_params->ep_info.pc = 337 pager_mem_params->image_info.image_base; 338 bl_mem_params->ep_info.args.arg0 = 339 paged_mem_params->image_info.image_base; 340 bl_mem_params->ep_info.args.arg1 = 0; /* Unused */ 341 bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */ 342 break; 343 344 case BL33_IMAGE_ID: 345 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); 346 assert(bl32_mem_params != NULL); 347 bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; 348 break; 349 350 default: 351 /* Do nothing in default case */ 352 break; 353 } 354 355 return err; 356 } 357 #endif 358