1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/desc_image_load.h> 16 #include <drivers/delay_timer.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/st/bsec.h> 19 #include <drivers/st/stm32_console.h> 20 #include <drivers/st/stm32_iwdg.h> 21 #include <drivers/st/stm32mp_pmic.h> 22 #include <drivers/st/stm32mp_reset.h> 23 #include <drivers/st/stm32mp1_clk.h> 24 #include <drivers/st/stm32mp1_pwr.h> 25 #include <drivers/st/stm32mp1_ram.h> 26 #include <lib/mmio.h> 27 #include <lib/optee_utils.h> 28 #include <lib/xlat_tables/xlat_tables_v2.h> 29 #include <plat/common/platform.h> 30 31 #include <stm32mp1_context.h> 32 #include <stm32mp1_dbgmcu.h> 33 34 static struct console_stm32 console; 35 36 static void print_reset_reason(void) 37 { 38 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR); 39 40 if (rstsr == 0U) { 41 WARN("Reset reason unknown\n"); 42 return; 43 } 44 45 INFO("Reset reason (0x%x):\n", rstsr); 46 47 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) { 48 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) { 49 INFO("System exits from STANDBY\n"); 50 return; 51 } 52 53 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) { 54 INFO("MPU exits from CSTANDBY\n"); 55 return; 56 } 57 } 58 59 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) { 60 INFO(" Power-on Reset (rst_por)\n"); 61 return; 62 } 63 64 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) { 65 INFO(" Brownout Reset (rst_bor)\n"); 66 return; 67 } 68 69 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) { 70 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 71 INFO(" System reset generated by MCU (MCSYSRST)\n"); 72 } else { 73 INFO(" Local reset generated by MCU (MCSYSRST)\n"); 74 } 75 return; 76 } 77 78 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) { 79 INFO(" System reset generated by MPU (MPSYSRST)\n"); 80 return; 81 } 82 83 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) { 84 INFO(" Reset due to a clock failure on HSE\n"); 85 return; 86 } 87 88 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) { 89 INFO(" IWDG1 Reset (rst_iwdg1)\n"); 90 return; 91 } 92 93 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) { 94 INFO(" IWDG2 Reset (rst_iwdg2)\n"); 95 return; 96 } 97 98 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) { 99 INFO(" MPU Processor 0 Reset\n"); 100 return; 101 } 102 103 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) { 104 INFO(" MPU Processor 1 Reset\n"); 105 return; 106 } 107 108 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 109 INFO(" Pad Reset from NRST\n"); 110 return; 111 } 112 113 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) { 114 INFO(" Reset due to a failure of VDD_CORE\n"); 115 return; 116 } 117 118 ERROR(" Unidentified reset reason\n"); 119 } 120 121 void bl2_el3_early_platform_setup(u_register_t arg0, 122 u_register_t arg1 __unused, 123 u_register_t arg2 __unused, 124 u_register_t arg3 __unused) 125 { 126 stm32mp_save_boot_ctx_address(arg0); 127 } 128 129 void bl2_platform_setup(void) 130 { 131 int ret; 132 133 if (dt_pmic_status() > 0) { 134 initialize_pmic(); 135 } 136 137 ret = stm32mp1_ddr_probe(); 138 if (ret < 0) { 139 ERROR("Invalid DDR init: error %d\n", ret); 140 panic(); 141 } 142 143 #ifdef AARCH32_SP_OPTEE 144 INFO("BL2 runs OP-TEE setup\n"); 145 /* Initialize tzc400 after DDR initialization */ 146 stm32mp1_security_setup(); 147 #else 148 INFO("BL2 runs SP_MIN setup\n"); 149 #endif 150 } 151 152 void bl2_el3_plat_arch_setup(void) 153 { 154 int32_t result; 155 struct dt_node_info dt_uart_info; 156 const char *board_model; 157 boot_api_context_t *boot_context = 158 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 159 uint32_t clk_rate; 160 uintptr_t pwr_base; 161 uintptr_t rcc_base; 162 163 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 164 BL_CODE_END - BL_CODE_BASE, 165 MT_CODE | MT_SECURE); 166 167 #ifdef AARCH32_SP_OPTEE 168 /* OP-TEE image needs post load processing: keep RAM read/write */ 169 mmap_add_region(STM32MP_DDR_BASE + dt_get_ddr_size() - 170 STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE, 171 STM32MP_DDR_BASE + dt_get_ddr_size() - 172 STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE, 173 STM32MP_DDR_S_SIZE, 174 MT_MEMORY | MT_RW | MT_SECURE); 175 176 mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE, 177 STM32MP_OPTEE_SIZE, 178 MT_MEMORY | MT_RW | MT_SECURE); 179 #else 180 /* Prevent corruption of preloaded BL32 */ 181 mmap_add_region(BL32_BASE, BL32_BASE, 182 BL32_LIMIT - BL32_BASE, 183 MT_MEMORY | MT_RO | MT_SECURE); 184 185 #endif 186 /* Map non secure DDR for BL33 load and DDR training area restore */ 187 mmap_add_region(STM32MP_DDR_BASE, 188 STM32MP_DDR_BASE, 189 STM32MP_DDR_MAX_SIZE, 190 MT_MEMORY | MT_RW | MT_NS); 191 192 /* Prevent corruption of preloaded Device Tree */ 193 mmap_add_region(DTB_BASE, DTB_BASE, 194 DTB_LIMIT - DTB_BASE, 195 MT_MEMORY | MT_RO | MT_SECURE); 196 197 configure_mmu(); 198 199 if (dt_open_and_check() < 0) { 200 panic(); 201 } 202 203 pwr_base = stm32mp_pwr_base(); 204 rcc_base = stm32mp_rcc_base(); 205 206 /* 207 * Disable the backup domain write protection. 208 * The protection is enable at each reset by hardware 209 * and must be disabled by software. 210 */ 211 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP); 212 213 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) { 214 ; 215 } 216 217 if (bsec_probe() != 0) { 218 panic(); 219 } 220 221 /* Reset backup domain on cold boot cases */ 222 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 223 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 224 225 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 226 0U) { 227 ; 228 } 229 230 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 231 } 232 233 /* Disable MCKPROT */ 234 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); 235 236 generic_delay_timer_init(); 237 238 if (stm32mp1_clk_probe() < 0) { 239 panic(); 240 } 241 242 if (stm32mp1_clk_init() < 0) { 243 panic(); 244 } 245 246 stm32mp1_syscfg_init(); 247 248 result = dt_get_stdout_uart_info(&dt_uart_info); 249 250 if ((result <= 0) || 251 (dt_uart_info.status == 0U) || 252 (dt_uart_info.clock < 0) || 253 (dt_uart_info.reset < 0)) { 254 goto skip_console_init; 255 } 256 257 if (dt_set_stdout_pinctrl() != 0) { 258 goto skip_console_init; 259 } 260 261 stm32mp_clk_enable((unsigned long)dt_uart_info.clock); 262 263 stm32mp_reset_assert((uint32_t)dt_uart_info.reset); 264 udelay(2); 265 stm32mp_reset_deassert((uint32_t)dt_uart_info.reset); 266 mdelay(1); 267 268 clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock); 269 270 if (console_stm32_register(dt_uart_info.base, clk_rate, 271 STM32MP_UART_BAUDRATE, &console) == 0) { 272 panic(); 273 } 274 275 stm32mp_print_cpuinfo(); 276 277 board_model = dt_get_board_model(); 278 if (board_model != NULL) { 279 NOTICE("Model: %s\n", board_model); 280 } 281 282 stm32mp_print_boardinfo(); 283 284 skip_console_init: 285 if (stm32_iwdg_init() < 0) { 286 panic(); 287 } 288 289 stm32_iwdg_refresh(); 290 291 result = stm32mp1_dbgmcu_freeze_iwdg2(); 292 if (result != 0) { 293 INFO("IWDG2 freeze error : %i\n", result); 294 } 295 296 if (stm32_save_boot_interface(boot_context->boot_interface_selected, 297 boot_context->boot_interface_instance) != 298 0) { 299 ERROR("Cannot save boot interface\n"); 300 } 301 302 stm32mp1_arch_security_setup(); 303 304 print_reset_reason(); 305 306 stm32mp_io_setup(); 307 } 308 309 #if defined(AARCH32_SP_OPTEE) 310 /******************************************************************************* 311 * This function can be used by the platforms to update/use image 312 * information for given `image_id`. 313 ******************************************************************************/ 314 int bl2_plat_handle_post_image_load(unsigned int image_id) 315 { 316 int err = 0; 317 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 318 bl_mem_params_node_t *bl32_mem_params; 319 bl_mem_params_node_t *pager_mem_params; 320 bl_mem_params_node_t *paged_mem_params; 321 322 assert(bl_mem_params != NULL); 323 324 switch (image_id) { 325 case BL32_IMAGE_ID: 326 bl_mem_params->ep_info.pc = 327 bl_mem_params->image_info.image_base; 328 329 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 330 assert(pager_mem_params != NULL); 331 pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE; 332 pager_mem_params->image_info.image_max_size = 333 STM32MP_OPTEE_SIZE; 334 335 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 336 assert(paged_mem_params != NULL); 337 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 338 (dt_get_ddr_size() - STM32MP_DDR_S_SIZE - 339 STM32MP_DDR_SHMEM_SIZE); 340 paged_mem_params->image_info.image_max_size = 341 STM32MP_DDR_S_SIZE; 342 343 err = parse_optee_header(&bl_mem_params->ep_info, 344 &pager_mem_params->image_info, 345 &paged_mem_params->image_info); 346 if (err) { 347 ERROR("OPTEE header parse error.\n"); 348 panic(); 349 } 350 351 /* Set optee boot info from parsed header data */ 352 bl_mem_params->ep_info.pc = 353 pager_mem_params->image_info.image_base; 354 bl_mem_params->ep_info.args.arg0 = 355 paged_mem_params->image_info.image_base; 356 bl_mem_params->ep_info.args.arg1 = 0; /* Unused */ 357 bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */ 358 break; 359 360 case BL33_IMAGE_ID: 361 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); 362 assert(bl32_mem_params != NULL); 363 bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; 364 break; 365 366 default: 367 /* Do nothing in default case */ 368 break; 369 } 370 371 return err; 372 } 373 #endif 374