1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/desc_image_load.h> 16 #include <drivers/delay_timer.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/st/stm32_console.h> 19 #include <drivers/st/stm32mp_pmic.h> 20 #include <drivers/st/stm32mp_reset.h> 21 #include <drivers/st/stm32mp1_clk.h> 22 #include <drivers/st/stm32mp1_pwr.h> 23 #include <drivers/st/stm32mp1_ram.h> 24 #include <lib/mmio.h> 25 #include <lib/xlat_tables/xlat_tables_v2.h> 26 #include <plat/common/platform.h> 27 28 #include <stm32mp1_context.h> 29 30 static struct console_stm32 console; 31 32 static void print_reset_reason(void) 33 { 34 uint32_t rstsr = mmio_read_32(RCC_BASE + RCC_MP_RSTSCLRR); 35 36 if (rstsr == 0U) { 37 WARN("Reset reason unknown\n"); 38 return; 39 } 40 41 INFO("Reset reason (0x%x):\n", rstsr); 42 43 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) { 44 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) { 45 INFO("System exits from STANDBY\n"); 46 return; 47 } 48 49 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) { 50 INFO("MPU exits from CSTANDBY\n"); 51 return; 52 } 53 } 54 55 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) { 56 INFO(" Power-on Reset (rst_por)\n"); 57 return; 58 } 59 60 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) { 61 INFO(" Brownout Reset (rst_bor)\n"); 62 return; 63 } 64 65 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) { 66 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 67 INFO(" System reset generated by MCU (MCSYSRST)\n"); 68 } else { 69 INFO(" Local reset generated by MCU (MCSYSRST)\n"); 70 } 71 return; 72 } 73 74 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) { 75 INFO(" System reset generated by MPU (MPSYSRST)\n"); 76 return; 77 } 78 79 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) { 80 INFO(" Reset due to a clock failure on HSE\n"); 81 return; 82 } 83 84 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) { 85 INFO(" IWDG1 Reset (rst_iwdg1)\n"); 86 return; 87 } 88 89 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) { 90 INFO(" IWDG2 Reset (rst_iwdg2)\n"); 91 return; 92 } 93 94 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) { 95 INFO(" MPU Processor 0 Reset\n"); 96 return; 97 } 98 99 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) { 100 INFO(" MPU Processor 1 Reset\n"); 101 return; 102 } 103 104 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 105 INFO(" Pad Reset from NRST\n"); 106 return; 107 } 108 109 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) { 110 INFO(" Reset due to a failure of VDD_CORE\n"); 111 return; 112 } 113 114 ERROR(" Unidentified reset reason\n"); 115 } 116 117 void bl2_el3_early_platform_setup(u_register_t arg0, 118 u_register_t arg1 __unused, 119 u_register_t arg2 __unused, 120 u_register_t arg3 __unused) 121 { 122 stm32mp_save_boot_ctx_address(arg0); 123 } 124 125 void bl2_platform_setup(void) 126 { 127 int ret; 128 129 if (dt_check_pmic()) { 130 initialize_pmic(); 131 } 132 133 ret = stm32mp1_ddr_probe(); 134 if (ret < 0) { 135 ERROR("Invalid DDR init: error %d\n", ret); 136 panic(); 137 } 138 139 INFO("BL2 runs SP_MIN setup\n"); 140 } 141 142 void bl2_el3_plat_arch_setup(void) 143 { 144 int32_t result; 145 struct dt_node_info dt_uart_info; 146 const char *board_model; 147 boot_api_context_t *boot_context = 148 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 149 uint32_t clk_rate; 150 151 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 152 BL_CODE_END - BL_CODE_BASE, 153 MT_CODE | MT_SECURE); 154 155 /* Prevent corruption of preloaded BL32 */ 156 mmap_add_region(BL32_BASE, BL32_BASE, 157 BL32_LIMIT - BL32_BASE, 158 MT_MEMORY | MT_RO | MT_SECURE); 159 160 /* Map non secure DDR for BL33 load and DDR training area restore */ 161 mmap_add_region(STM32MP_DDR_BASE, 162 STM32MP_DDR_BASE, 163 STM32MP_DDR_MAX_SIZE, 164 MT_MEMORY | MT_RW | MT_NS); 165 166 /* Prevent corruption of preloaded Device Tree */ 167 mmap_add_region(DTB_BASE, DTB_BASE, 168 DTB_LIMIT - DTB_BASE, 169 MT_MEMORY | MT_RO | MT_SECURE); 170 171 configure_mmu(); 172 173 if (dt_open_and_check() < 0) { 174 panic(); 175 } 176 177 /* 178 * Disable the backup domain write protection. 179 * The protection is enable at each reset by hardware 180 * and must be disabled by software. 181 */ 182 mmio_setbits_32(PWR_BASE + PWR_CR1, PWR_CR1_DBP); 183 184 while ((mmio_read_32(PWR_BASE + PWR_CR1) & PWR_CR1_DBP) == 0U) { 185 ; 186 } 187 188 /* Reset backup domain on cold boot cases */ 189 if ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 190 mmio_setbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); 191 192 while ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_VSWRST) == 193 0U) { 194 ; 195 } 196 197 mmio_clrbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); 198 } 199 200 generic_delay_timer_init(); 201 202 if (stm32mp1_clk_probe() < 0) { 203 panic(); 204 } 205 206 if (stm32mp1_clk_init() < 0) { 207 panic(); 208 } 209 210 result = dt_get_stdout_uart_info(&dt_uart_info); 211 212 if ((result <= 0) || 213 (dt_uart_info.status == 0U) || 214 (dt_uart_info.clock < 0) || 215 (dt_uart_info.reset < 0)) { 216 goto skip_console_init; 217 } 218 219 if (dt_set_stdout_pinctrl() != 0) { 220 goto skip_console_init; 221 } 222 223 if (stm32mp_clk_enable((unsigned long)dt_uart_info.clock) != 0) { 224 goto skip_console_init; 225 } 226 227 stm32mp_reset_assert((uint32_t)dt_uart_info.reset); 228 udelay(2); 229 stm32mp_reset_deassert((uint32_t)dt_uart_info.reset); 230 mdelay(1); 231 232 clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock); 233 234 if (console_stm32_register(dt_uart_info.base, clk_rate, 235 STM32MP_UART_BAUDRATE, &console) == 0) { 236 panic(); 237 } 238 239 board_model = dt_get_board_model(); 240 if (board_model != NULL) { 241 NOTICE("Model: %s\n", board_model); 242 } 243 244 skip_console_init: 245 246 if (stm32_save_boot_interface(boot_context->boot_interface_selected, 247 boot_context->boot_interface_instance) != 248 0) { 249 ERROR("Cannot save boot interface\n"); 250 } 251 252 stm32mp1_arch_security_setup(); 253 254 print_reset_reason(); 255 256 stm32mp_io_setup(); 257 } 258