1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <boot_api.h> 11 #include <debug.h> 12 #include <delay_timer.h> 13 #include <desc_image_load.h> 14 #include <generic_delay_timer.h> 15 #include <mmio.h> 16 #include <platform.h> 17 #include <platform_def.h> 18 #include <stm32_console.h> 19 #include <stm32mp1_clk.h> 20 #include <stm32mp1_context.h> 21 #include <stm32mp1_dt.h> 22 #include <stm32mp1_pmic.h> 23 #include <stm32mp1_private.h> 24 #include <stm32mp1_pwr.h> 25 #include <stm32mp1_ram.h> 26 #include <stm32mp1_rcc.h> 27 #include <stm32mp1_reset.h> 28 #include <string.h> 29 #include <xlat_tables_v2.h> 30 31 static struct console_stm32 console; 32 33 void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1, 34 u_register_t arg2, u_register_t arg3) 35 { 36 stm32mp1_save_boot_ctx_address(arg0); 37 } 38 39 void bl2_platform_setup(void) 40 { 41 int ret; 42 43 if (dt_check_pmic()) { 44 initialize_pmic(); 45 } 46 47 ret = stm32mp1_ddr_probe(); 48 if (ret < 0) { 49 ERROR("Invalid DDR init: error %d\n", ret); 50 panic(); 51 } 52 53 INFO("BL2 runs SP_MIN setup\n"); 54 } 55 56 void bl2_el3_plat_arch_setup(void) 57 { 58 int32_t result; 59 struct dt_node_info dt_dev_info; 60 const char *board_model; 61 boot_api_context_t *boot_context = 62 (boot_api_context_t *)stm32mp1_get_boot_ctx_address(); 63 uint32_t clk_rate; 64 65 /* 66 * Disable the backup domain write protection. 67 * The protection is enable at each reset by hardware 68 * and must be disabled by software. 69 */ 70 mmio_setbits_32(PWR_BASE + PWR_CR1, PWR_CR1_DBP); 71 72 while ((mmio_read_32(PWR_BASE + PWR_CR1) & PWR_CR1_DBP) == 0U) { 73 ; 74 } 75 76 /* Reset backup domain on cold boot cases */ 77 if ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 78 mmio_setbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); 79 80 while ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_VSWRST) == 81 0U) { 82 ; 83 } 84 85 mmio_clrbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); 86 } 87 88 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 89 BL_CODE_END - BL_CODE_BASE, 90 MT_CODE | MT_SECURE); 91 92 /* Prevent corruption of preloaded BL32 */ 93 mmap_add_region(BL32_BASE, BL32_BASE, 94 BL32_LIMIT - BL32_BASE, 95 MT_MEMORY | MT_RO | MT_SECURE); 96 97 /* Prevent corruption of preloaded Device Tree */ 98 mmap_add_region(DTB_BASE, DTB_BASE, 99 DTB_LIMIT - DTB_BASE, 100 MT_MEMORY | MT_RO | MT_SECURE); 101 102 configure_mmu(); 103 104 generic_delay_timer_init(); 105 106 if (dt_open_and_check() < 0) { 107 panic(); 108 } 109 110 if (stm32mp1_clk_probe() < 0) { 111 panic(); 112 } 113 114 if (stm32mp1_clk_init() < 0) { 115 panic(); 116 } 117 118 result = dt_get_stdout_uart_info(&dt_dev_info); 119 120 if ((result <= 0) || 121 (dt_dev_info.status == 0U) || 122 (dt_dev_info.clock < 0) || 123 (dt_dev_info.reset < 0)) { 124 goto skip_console_init; 125 } 126 127 if (dt_set_stdout_pinctrl() != 0) { 128 goto skip_console_init; 129 } 130 131 if (stm32mp1_clk_enable((unsigned long)dt_dev_info.clock) != 0) { 132 goto skip_console_init; 133 } 134 135 stm32mp1_reset_assert((uint32_t)dt_dev_info.reset); 136 udelay(2); 137 stm32mp1_reset_deassert((uint32_t)dt_dev_info.reset); 138 mdelay(1); 139 140 clk_rate = stm32mp1_clk_get_rate((unsigned long)dt_dev_info.clock); 141 142 if (console_stm32_register(dt_dev_info.base, clk_rate, 143 STM32MP1_UART_BAUDRATE, &console) == 0) { 144 panic(); 145 } 146 147 board_model = dt_get_board_model(); 148 if (board_model != NULL) { 149 NOTICE("%s\n", board_model); 150 } 151 152 skip_console_init: 153 154 if (stm32_save_boot_interface(boot_context->boot_interface_selected, 155 boot_context->boot_interface_instance) != 156 0) { 157 ERROR("Cannot save boot interface\n"); 158 } 159 160 stm32mp1_arch_security_setup(); 161 162 stm32mp1_io_setup(); 163 } 164