1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/desc_image_load.h> 16 #include <drivers/delay_timer.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/st/stm32_console.h> 19 #include <drivers/st/stm32mp_pmic.h> 20 #include <drivers/st/stm32mp1_clk.h> 21 #include <drivers/st/stm32mp1_pwr.h> 22 #include <drivers/st/stm32mp1_ram.h> 23 #include <drivers/st/stm32mp1_rcc.h> 24 #include <drivers/st/stm32mp1_reset.h> 25 #include <lib/mmio.h> 26 #include <lib/xlat_tables/xlat_tables_v2.h> 27 #include <plat/common/platform.h> 28 29 #include <boot_api.h> 30 #include <stm32mp1_context.h> 31 #include <stm32mp1_dt.h> 32 #include <stm32mp1_private.h> 33 34 static struct console_stm32 console; 35 36 void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1, 37 u_register_t arg2, u_register_t arg3) 38 { 39 stm32mp1_save_boot_ctx_address(arg0); 40 } 41 42 void bl2_platform_setup(void) 43 { 44 int ret; 45 46 if (dt_check_pmic()) { 47 initialize_pmic(); 48 } 49 50 ret = stm32mp1_ddr_probe(); 51 if (ret < 0) { 52 ERROR("Invalid DDR init: error %d\n", ret); 53 panic(); 54 } 55 56 INFO("BL2 runs SP_MIN setup\n"); 57 } 58 59 void bl2_el3_plat_arch_setup(void) 60 { 61 int32_t result; 62 struct dt_node_info dt_dev_info; 63 const char *board_model; 64 boot_api_context_t *boot_context = 65 (boot_api_context_t *)stm32mp1_get_boot_ctx_address(); 66 uint32_t clk_rate; 67 68 /* 69 * Disable the backup domain write protection. 70 * The protection is enable at each reset by hardware 71 * and must be disabled by software. 72 */ 73 mmio_setbits_32(PWR_BASE + PWR_CR1, PWR_CR1_DBP); 74 75 while ((mmio_read_32(PWR_BASE + PWR_CR1) & PWR_CR1_DBP) == 0U) { 76 ; 77 } 78 79 /* Reset backup domain on cold boot cases */ 80 if ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 81 mmio_setbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); 82 83 while ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_VSWRST) == 84 0U) { 85 ; 86 } 87 88 mmio_clrbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); 89 } 90 91 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 92 BL_CODE_END - BL_CODE_BASE, 93 MT_CODE | MT_SECURE); 94 95 /* Prevent corruption of preloaded BL32 */ 96 mmap_add_region(BL32_BASE, BL32_BASE, 97 BL32_LIMIT - BL32_BASE, 98 MT_MEMORY | MT_RO | MT_SECURE); 99 100 /* Prevent corruption of preloaded Device Tree */ 101 mmap_add_region(DTB_BASE, DTB_BASE, 102 DTB_LIMIT - DTB_BASE, 103 MT_MEMORY | MT_RO | MT_SECURE); 104 105 configure_mmu(); 106 107 generic_delay_timer_init(); 108 109 if (dt_open_and_check() < 0) { 110 panic(); 111 } 112 113 if (stm32mp1_clk_probe() < 0) { 114 panic(); 115 } 116 117 if (stm32mp1_clk_init() < 0) { 118 panic(); 119 } 120 121 result = dt_get_stdout_uart_info(&dt_dev_info); 122 123 if ((result <= 0) || 124 (dt_dev_info.status == 0U) || 125 (dt_dev_info.clock < 0) || 126 (dt_dev_info.reset < 0)) { 127 goto skip_console_init; 128 } 129 130 if (dt_set_stdout_pinctrl() != 0) { 131 goto skip_console_init; 132 } 133 134 if (stm32mp1_clk_enable((unsigned long)dt_dev_info.clock) != 0) { 135 goto skip_console_init; 136 } 137 138 stm32mp1_reset_assert((uint32_t)dt_dev_info.reset); 139 udelay(2); 140 stm32mp1_reset_deassert((uint32_t)dt_dev_info.reset); 141 mdelay(1); 142 143 clk_rate = stm32mp1_clk_get_rate((unsigned long)dt_dev_info.clock); 144 145 if (console_stm32_register(dt_dev_info.base, clk_rate, 146 STM32MP1_UART_BAUDRATE, &console) == 0) { 147 panic(); 148 } 149 150 board_model = dt_get_board_model(); 151 if (board_model != NULL) { 152 NOTICE("%s\n", board_model); 153 } 154 155 skip_console_init: 156 157 if (stm32_save_boot_interface(boot_context->boot_interface_selected, 158 boot_context->boot_interface_instance) != 159 0) { 160 ERROR("Cannot save boot interface\n"); 161 } 162 163 stm32mp1_arch_security_setup(); 164 165 stm32mp1_io_setup(); 166 } 167