1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/desc_image_load.h> 17 #include <drivers/delay_timer.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <drivers/mmc.h> 20 #include <drivers/st/bsec.h> 21 #include <drivers/st/stm32_console.h> 22 #include <drivers/st/stm32_iwdg.h> 23 #include <drivers/st/stm32mp_pmic.h> 24 #include <drivers/st/stm32mp_reset.h> 25 #include <drivers/st/stm32mp1_clk.h> 26 #include <drivers/st/stm32mp1_pwr.h> 27 #include <drivers/st/stm32mp1_ram.h> 28 #include <lib/fconf/fconf.h> 29 #include <lib/fconf/fconf_dyn_cfg_getter.h> 30 #include <lib/mmio.h> 31 #include <lib/optee_utils.h> 32 #include <lib/xlat_tables/xlat_tables_v2.h> 33 #include <plat/common/platform.h> 34 35 #include <stm32mp1_context.h> 36 #include <stm32mp1_dbgmcu.h> 37 38 #define RESET_TIMEOUT_US_1MS 1000U 39 40 static console_t console; 41 static struct stm32mp_auth_ops stm32mp1_auth_ops; 42 43 static void print_reset_reason(void) 44 { 45 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR); 46 47 if (rstsr == 0U) { 48 WARN("Reset reason unknown\n"); 49 return; 50 } 51 52 INFO("Reset reason (0x%x):\n", rstsr); 53 54 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) { 55 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) { 56 INFO("System exits from STANDBY\n"); 57 return; 58 } 59 60 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) { 61 INFO("MPU exits from CSTANDBY\n"); 62 return; 63 } 64 } 65 66 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) { 67 INFO(" Power-on Reset (rst_por)\n"); 68 return; 69 } 70 71 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) { 72 INFO(" Brownout Reset (rst_bor)\n"); 73 return; 74 } 75 76 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) { 77 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 78 INFO(" System reset generated by MCU (MCSYSRST)\n"); 79 } else { 80 INFO(" Local reset generated by MCU (MCSYSRST)\n"); 81 } 82 return; 83 } 84 85 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) { 86 INFO(" System reset generated by MPU (MPSYSRST)\n"); 87 return; 88 } 89 90 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) { 91 INFO(" Reset due to a clock failure on HSE\n"); 92 return; 93 } 94 95 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) { 96 INFO(" IWDG1 Reset (rst_iwdg1)\n"); 97 return; 98 } 99 100 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) { 101 INFO(" IWDG2 Reset (rst_iwdg2)\n"); 102 return; 103 } 104 105 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) { 106 INFO(" MPU Processor 0 Reset\n"); 107 return; 108 } 109 110 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) { 111 INFO(" MPU Processor 1 Reset\n"); 112 return; 113 } 114 115 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 116 INFO(" Pad Reset from NRST\n"); 117 return; 118 } 119 120 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) { 121 INFO(" Reset due to a failure of VDD_CORE\n"); 122 return; 123 } 124 125 ERROR(" Unidentified reset reason\n"); 126 } 127 128 void bl2_el3_early_platform_setup(u_register_t arg0, 129 u_register_t arg1 __unused, 130 u_register_t arg2 __unused, 131 u_register_t arg3 __unused) 132 { 133 stm32mp_save_boot_ctx_address(arg0); 134 } 135 136 void bl2_platform_setup(void) 137 { 138 int ret; 139 140 if (dt_pmic_status() > 0) { 141 initialize_pmic(); 142 } 143 144 ret = stm32mp1_ddr_probe(); 145 if (ret < 0) { 146 ERROR("Invalid DDR init: error %d\n", ret); 147 panic(); 148 } 149 150 /* Map DDR for binary load, now with cacheable attribute */ 151 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, 152 STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE); 153 if (ret < 0) { 154 ERROR("DDR mapping: error %d\n", ret); 155 panic(); 156 } 157 158 #if STM32MP_USE_STM32IMAGE 159 #ifdef AARCH32_SP_OPTEE 160 INFO("BL2 runs OP-TEE setup\n"); 161 #else 162 INFO("BL2 runs SP_MIN setup\n"); 163 #endif 164 #endif /* STM32MP_USE_STM32IMAGE */ 165 } 166 167 void bl2_el3_plat_arch_setup(void) 168 { 169 int32_t result; 170 struct dt_node_info dt_uart_info; 171 const char *board_model; 172 boot_api_context_t *boot_context = 173 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 174 uint32_t clk_rate; 175 uintptr_t pwr_base; 176 uintptr_t rcc_base; 177 178 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 179 BL_CODE_END - BL_CODE_BASE, 180 MT_CODE | MT_SECURE); 181 182 #if STM32MP_USE_STM32IMAGE 183 #ifdef AARCH32_SP_OPTEE 184 mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE, 185 STM32MP_OPTEE_SIZE, 186 MT_MEMORY | MT_RW | MT_SECURE); 187 #else 188 /* Prevent corruption of preloaded BL32 */ 189 mmap_add_region(BL32_BASE, BL32_BASE, 190 BL32_LIMIT - BL32_BASE, 191 MT_RO_DATA | MT_SECURE); 192 #endif 193 #endif /* STM32MP_USE_STM32IMAGE */ 194 195 /* Prevent corruption of preloaded Device Tree */ 196 mmap_add_region(DTB_BASE, DTB_BASE, 197 DTB_LIMIT - DTB_BASE, 198 MT_RO_DATA | MT_SECURE); 199 200 configure_mmu(); 201 202 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) { 203 panic(); 204 } 205 206 pwr_base = stm32mp_pwr_base(); 207 rcc_base = stm32mp_rcc_base(); 208 209 /* 210 * Disable the backup domain write protection. 211 * The protection is enable at each reset by hardware 212 * and must be disabled by software. 213 */ 214 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP); 215 216 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) { 217 ; 218 } 219 220 if (bsec_probe() != 0) { 221 panic(); 222 } 223 224 /* Reset backup domain on cold boot cases */ 225 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 226 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 227 228 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 229 0U) { 230 ; 231 } 232 233 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 234 } 235 236 /* Disable MCKPROT */ 237 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); 238 239 generic_delay_timer_init(); 240 241 if (stm32mp1_clk_probe() < 0) { 242 panic(); 243 } 244 245 if (stm32mp1_clk_init() < 0) { 246 panic(); 247 } 248 249 stm32mp1_syscfg_init(); 250 251 result = dt_get_stdout_uart_info(&dt_uart_info); 252 253 if ((result <= 0) || 254 (dt_uart_info.status == 0U) || 255 (dt_uart_info.clock < 0) || 256 (dt_uart_info.reset < 0)) { 257 goto skip_console_init; 258 } 259 260 if (dt_set_stdout_pinctrl() != 0) { 261 goto skip_console_init; 262 } 263 264 stm32mp_clk_enable((unsigned long)dt_uart_info.clock); 265 266 if (stm32mp_reset_assert((uint32_t)dt_uart_info.reset, 267 RESET_TIMEOUT_US_1MS) != 0) { 268 panic(); 269 } 270 271 udelay(2); 272 273 if (stm32mp_reset_deassert((uint32_t)dt_uart_info.reset, 274 RESET_TIMEOUT_US_1MS) != 0) { 275 panic(); 276 } 277 278 mdelay(1); 279 280 clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock); 281 282 if (console_stm32_register(dt_uart_info.base, clk_rate, 283 STM32MP_UART_BAUDRATE, &console) == 0) { 284 panic(); 285 } 286 287 console_set_scope(&console, CONSOLE_FLAG_BOOT | 288 CONSOLE_FLAG_CRASH | CONSOLE_FLAG_TRANSLATE_CRLF); 289 290 stm32mp_print_cpuinfo(); 291 292 board_model = dt_get_board_model(); 293 if (board_model != NULL) { 294 NOTICE("Model: %s\n", board_model); 295 } 296 297 stm32mp_print_boardinfo(); 298 299 if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) { 300 NOTICE("Bootrom authentication %s\n", 301 (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ? 302 "failed" : "succeeded"); 303 } 304 305 skip_console_init: 306 if (stm32_iwdg_init() < 0) { 307 panic(); 308 } 309 310 stm32_iwdg_refresh(); 311 312 result = stm32mp1_dbgmcu_freeze_iwdg2(); 313 if (result != 0) { 314 INFO("IWDG2 freeze error : %i\n", result); 315 } 316 317 if (stm32_save_boot_interface(boot_context->boot_interface_selected, 318 boot_context->boot_interface_instance) != 319 0) { 320 ERROR("Cannot save boot interface\n"); 321 } 322 323 stm32mp1_auth_ops.check_key = boot_context->bootrom_ecdsa_check_key; 324 stm32mp1_auth_ops.verify_signature = 325 boot_context->bootrom_ecdsa_verify_signature; 326 327 stm32mp_init_auth(&stm32mp1_auth_ops); 328 329 stm32mp1_arch_security_setup(); 330 331 print_reset_reason(); 332 333 #if !STM32MP_USE_STM32IMAGE 334 fconf_populate("TB_FW", STM32MP_DTB_BASE); 335 #endif /* !STM32MP_USE_STM32IMAGE */ 336 337 stm32mp_io_setup(); 338 } 339 340 /******************************************************************************* 341 * This function can be used by the platforms to update/use image 342 * information for given `image_id`. 343 ******************************************************************************/ 344 int bl2_plat_handle_post_image_load(unsigned int image_id) 345 { 346 int err = 0; 347 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 348 bl_mem_params_node_t *bl32_mem_params; 349 bl_mem_params_node_t *pager_mem_params __unused; 350 bl_mem_params_node_t *paged_mem_params __unused; 351 #if !STM32MP_USE_STM32IMAGE 352 const struct dyn_cfg_dtb_info_t *config_info; 353 bl_mem_params_node_t *tos_fw_mem_params; 354 unsigned int i; 355 unsigned int idx; 356 unsigned long long ddr_top __unused; 357 const unsigned int image_ids[] = { 358 BL32_IMAGE_ID, 359 BL33_IMAGE_ID, 360 HW_CONFIG_ID, 361 TOS_FW_CONFIG_ID, 362 }; 363 #endif /* !STM32MP_USE_STM32IMAGE */ 364 365 assert(bl_mem_params != NULL); 366 367 switch (image_id) { 368 #if !STM32MP_USE_STM32IMAGE 369 case FW_CONFIG_ID: 370 /* Set global DTB info for fixed fw_config information */ 371 set_config_info(STM32MP_FW_CONFIG_BASE, STM32MP_FW_CONFIG_MAX_SIZE, FW_CONFIG_ID); 372 fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE); 373 374 idx = dyn_cfg_dtb_info_get_index(TOS_FW_CONFIG_ID); 375 376 /* Iterate through all the fw config IDs */ 377 for (i = 0U; i < ARRAY_SIZE(image_ids); i++) { 378 if ((image_ids[i] == TOS_FW_CONFIG_ID) && (idx == FCONF_INVALID_IDX)) { 379 continue; 380 } 381 382 bl_mem_params = get_bl_mem_params_node(image_ids[i]); 383 assert(bl_mem_params != NULL); 384 385 config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]); 386 if (config_info == NULL) { 387 continue; 388 } 389 390 bl_mem_params->image_info.image_base = config_info->config_addr; 391 bl_mem_params->image_info.image_max_size = config_info->config_max_size; 392 393 bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING; 394 395 switch (image_ids[i]) { 396 case BL32_IMAGE_ID: 397 bl_mem_params->ep_info.pc = config_info->config_addr; 398 399 /* In case of OPTEE, initialize address space with tos_fw addr */ 400 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 401 pager_mem_params->image_info.image_base = config_info->config_addr; 402 pager_mem_params->image_info.image_max_size = 403 config_info->config_max_size; 404 405 /* Init base and size for pager if exist */ 406 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 407 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 408 (dt_get_ddr_size() - STM32MP_DDR_S_SIZE - 409 STM32MP_DDR_SHMEM_SIZE); 410 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; 411 break; 412 413 case BL33_IMAGE_ID: 414 bl_mem_params->ep_info.pc = config_info->config_addr; 415 break; 416 417 case HW_CONFIG_ID: 418 case TOS_FW_CONFIG_ID: 419 break; 420 421 default: 422 return -EINVAL; 423 } 424 } 425 break; 426 #endif /* !STM32MP_USE_STM32IMAGE */ 427 428 case BL32_IMAGE_ID: 429 if (optee_header_is_valid(bl_mem_params->image_info.image_base)) { 430 /* BL32 is OP-TEE header */ 431 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 432 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 433 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 434 assert((pager_mem_params != NULL) && (paged_mem_params != NULL)); 435 436 #if STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) 437 /* Set OP-TEE extra image load areas at run-time */ 438 pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE; 439 pager_mem_params->image_info.image_max_size = STM32MP_OPTEE_SIZE; 440 441 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 442 dt_get_ddr_size() - 443 STM32MP_DDR_S_SIZE - 444 STM32MP_DDR_SHMEM_SIZE; 445 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; 446 #endif /* STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) */ 447 448 err = parse_optee_header(&bl_mem_params->ep_info, 449 &pager_mem_params->image_info, 450 &paged_mem_params->image_info); 451 if (err) { 452 ERROR("OPTEE header parse error.\n"); 453 panic(); 454 } 455 456 /* Set optee boot info from parsed header data */ 457 bl_mem_params->ep_info.args.arg0 = paged_mem_params->image_info.image_base; 458 bl_mem_params->ep_info.args.arg1 = 0; /* Unused */ 459 bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */ 460 } else { 461 #if !STM32MP_USE_STM32IMAGE 462 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 463 tos_fw_mem_params = get_bl_mem_params_node(TOS_FW_CONFIG_ID); 464 bl_mem_params->image_info.image_max_size += 465 tos_fw_mem_params->image_info.image_max_size; 466 #endif /* !STM32MP_USE_STM32IMAGE */ 467 bl_mem_params->ep_info.args.arg0 = 0; 468 } 469 break; 470 471 case BL33_IMAGE_ID: 472 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); 473 assert(bl32_mem_params != NULL); 474 bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; 475 break; 476 477 default: 478 /* Do nothing in default case */ 479 break; 480 } 481 482 #if STM32MP_SDMMC || STM32MP_EMMC 483 /* 484 * Invalidate remaining data read from MMC but not flushed by load_image_flush(). 485 * We take the worst case which is 2 MMC blocks. 486 */ 487 if ((image_id != FW_CONFIG_ID) && 488 ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) { 489 inv_dcache_range(bl_mem_params->image_info.image_base + 490 bl_mem_params->image_info.image_size, 491 2U * MMC_BLOCK_SIZE); 492 } 493 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 494 495 return err; 496 } 497 498 void bl2_el3_plat_prepare_exit(void) 499 { 500 uint16_t boot_itf = stm32mp_get_boot_itf_selected(); 501 502 switch (boot_itf) { 503 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 504 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART: 505 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 506 /* Invalidate the downloaded buffer used with io_memmap */ 507 inv_dcache_range(DWL_BUFFER_BASE, DWL_BUFFER_SIZE); 508 break; 509 #endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */ 510 default: 511 /* Do nothing in default case */ 512 break; 513 } 514 515 stm32mp1_security_setup(); 516 } 517