1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/desc_image_load.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/mmc.h> 19 #include <drivers/st/bsec.h> 20 #include <drivers/st/stm32_iwdg.h> 21 #include <drivers/st/stm32_uart.h> 22 #include <drivers/st/stm32mp_pmic.h> 23 #include <drivers/st/stm32mp1_clk.h> 24 #include <drivers/st/stm32mp1_pwr.h> 25 #include <drivers/st/stm32mp1_ram.h> 26 #include <lib/fconf/fconf.h> 27 #include <lib/fconf/fconf_dyn_cfg_getter.h> 28 #include <lib/mmio.h> 29 #include <lib/optee_utils.h> 30 #include <lib/xlat_tables/xlat_tables_v2.h> 31 #include <plat/common/platform.h> 32 33 #include <stm32mp1_dbgmcu.h> 34 35 static struct stm32mp_auth_ops stm32mp1_auth_ops; 36 37 static void print_reset_reason(void) 38 { 39 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR); 40 41 if (rstsr == 0U) { 42 WARN("Reset reason unknown\n"); 43 return; 44 } 45 46 INFO("Reset reason (0x%x):\n", rstsr); 47 48 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) { 49 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) { 50 INFO("System exits from STANDBY\n"); 51 return; 52 } 53 54 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) { 55 INFO("MPU exits from CSTANDBY\n"); 56 return; 57 } 58 } 59 60 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) { 61 INFO(" Power-on Reset (rst_por)\n"); 62 return; 63 } 64 65 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) { 66 INFO(" Brownout Reset (rst_bor)\n"); 67 return; 68 } 69 70 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) { 71 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 72 INFO(" System reset generated by MCU (MCSYSRST)\n"); 73 } else { 74 INFO(" Local reset generated by MCU (MCSYSRST)\n"); 75 } 76 return; 77 } 78 79 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) { 80 INFO(" System reset generated by MPU (MPSYSRST)\n"); 81 return; 82 } 83 84 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) { 85 INFO(" Reset due to a clock failure on HSE\n"); 86 return; 87 } 88 89 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) { 90 INFO(" IWDG1 Reset (rst_iwdg1)\n"); 91 return; 92 } 93 94 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) { 95 INFO(" IWDG2 Reset (rst_iwdg2)\n"); 96 return; 97 } 98 99 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) { 100 INFO(" MPU Processor 0 Reset\n"); 101 return; 102 } 103 104 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) { 105 INFO(" MPU Processor 1 Reset\n"); 106 return; 107 } 108 109 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 110 INFO(" Pad Reset from NRST\n"); 111 return; 112 } 113 114 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) { 115 INFO(" Reset due to a failure of VDD_CORE\n"); 116 return; 117 } 118 119 ERROR(" Unidentified reset reason\n"); 120 } 121 122 void bl2_el3_early_platform_setup(u_register_t arg0, 123 u_register_t arg1 __unused, 124 u_register_t arg2 __unused, 125 u_register_t arg3 __unused) 126 { 127 stm32mp_save_boot_ctx_address(arg0); 128 } 129 130 void bl2_platform_setup(void) 131 { 132 int ret; 133 134 if (dt_pmic_status() > 0) { 135 initialize_pmic(); 136 } 137 138 ret = stm32mp1_ddr_probe(); 139 if (ret < 0) { 140 ERROR("Invalid DDR init: error %d\n", ret); 141 panic(); 142 } 143 144 /* Map DDR for binary load, now with cacheable attribute */ 145 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, 146 STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE); 147 if (ret < 0) { 148 ERROR("DDR mapping: error %d\n", ret); 149 panic(); 150 } 151 152 #if STM32MP_USE_STM32IMAGE 153 #ifdef AARCH32_SP_OPTEE 154 INFO("BL2 runs OP-TEE setup\n"); 155 #else 156 INFO("BL2 runs SP_MIN setup\n"); 157 #endif 158 #endif /* STM32MP_USE_STM32IMAGE */ 159 } 160 161 void bl2_el3_plat_arch_setup(void) 162 { 163 int32_t result; 164 const char *board_model; 165 boot_api_context_t *boot_context = 166 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 167 uintptr_t pwr_base; 168 uintptr_t rcc_base; 169 170 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 171 BL_CODE_END - BL_CODE_BASE, 172 MT_CODE | MT_SECURE); 173 174 #if STM32MP_USE_STM32IMAGE 175 #ifdef AARCH32_SP_OPTEE 176 mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE, 177 STM32MP_OPTEE_SIZE, 178 MT_MEMORY | MT_RW | MT_SECURE); 179 #else 180 /* Prevent corruption of preloaded BL32 */ 181 mmap_add_region(BL32_BASE, BL32_BASE, 182 BL32_LIMIT - BL32_BASE, 183 MT_RO_DATA | MT_SECURE); 184 #endif 185 #endif /* STM32MP_USE_STM32IMAGE */ 186 187 /* Prevent corruption of preloaded Device Tree */ 188 mmap_add_region(DTB_BASE, DTB_BASE, 189 DTB_LIMIT - DTB_BASE, 190 MT_RO_DATA | MT_SECURE); 191 192 configure_mmu(); 193 194 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) { 195 panic(); 196 } 197 198 pwr_base = stm32mp_pwr_base(); 199 rcc_base = stm32mp_rcc_base(); 200 201 /* 202 * Disable the backup domain write protection. 203 * The protection is enable at each reset by hardware 204 * and must be disabled by software. 205 */ 206 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP); 207 208 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) { 209 ; 210 } 211 212 if (bsec_probe() != 0) { 213 panic(); 214 } 215 216 /* Reset backup domain on cold boot cases */ 217 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 218 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 219 220 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 221 0U) { 222 ; 223 } 224 225 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 226 } 227 228 /* Disable MCKPROT */ 229 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); 230 231 generic_delay_timer_init(); 232 233 #if STM32MP_UART_PROGRAMMER 234 /* Disable programmer UART before changing clock tree */ 235 if (boot_context->boot_interface_selected == 236 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) { 237 uintptr_t uart_prog_addr = 238 get_uart_address(boot_context->boot_interface_instance); 239 240 stm32_uart_stop(uart_prog_addr); 241 } 242 #endif 243 if (stm32mp1_clk_probe() < 0) { 244 panic(); 245 } 246 247 if (stm32mp1_clk_init() < 0) { 248 panic(); 249 } 250 251 stm32mp1_syscfg_init(); 252 253 stm32_save_boot_interface(boot_context->boot_interface_selected, 254 boot_context->boot_interface_instance); 255 256 #if STM32MP_USB_PROGRAMMER 257 /* Deconfigure all UART RX pins configured by ROM code */ 258 stm32mp1_deconfigure_uart_pins(); 259 #endif 260 261 if (stm32mp_uart_console_setup() != 0) { 262 goto skip_console_init; 263 } 264 265 stm32mp_print_cpuinfo(); 266 267 board_model = dt_get_board_model(); 268 if (board_model != NULL) { 269 NOTICE("Model: %s\n", board_model); 270 } 271 272 stm32mp_print_boardinfo(); 273 274 if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) { 275 NOTICE("Bootrom authentication %s\n", 276 (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ? 277 "failed" : "succeeded"); 278 } 279 280 skip_console_init: 281 if (stm32_iwdg_init() < 0) { 282 panic(); 283 } 284 285 stm32_iwdg_refresh(); 286 287 result = stm32mp1_dbgmcu_freeze_iwdg2(); 288 if (result != 0) { 289 INFO("IWDG2 freeze error : %i\n", result); 290 } 291 292 stm32mp1_auth_ops.check_key = boot_context->bootrom_ecdsa_check_key; 293 stm32mp1_auth_ops.verify_signature = 294 boot_context->bootrom_ecdsa_verify_signature; 295 296 stm32mp_init_auth(&stm32mp1_auth_ops); 297 298 stm32mp1_arch_security_setup(); 299 300 print_reset_reason(); 301 302 #if !STM32MP_USE_STM32IMAGE 303 fconf_populate("TB_FW", STM32MP_DTB_BASE); 304 #endif /* !STM32MP_USE_STM32IMAGE */ 305 306 stm32mp_io_setup(); 307 } 308 309 /******************************************************************************* 310 * This function can be used by the platforms to update/use image 311 * information for given `image_id`. 312 ******************************************************************************/ 313 int bl2_plat_handle_post_image_load(unsigned int image_id) 314 { 315 int err = 0; 316 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 317 bl_mem_params_node_t *bl32_mem_params; 318 bl_mem_params_node_t *pager_mem_params __unused; 319 bl_mem_params_node_t *paged_mem_params __unused; 320 #if !STM32MP_USE_STM32IMAGE 321 const struct dyn_cfg_dtb_info_t *config_info; 322 bl_mem_params_node_t *tos_fw_mem_params; 323 unsigned int i; 324 unsigned long long ddr_top __unused; 325 const unsigned int image_ids[] = { 326 BL32_IMAGE_ID, 327 BL33_IMAGE_ID, 328 HW_CONFIG_ID, 329 TOS_FW_CONFIG_ID, 330 }; 331 #endif /* !STM32MP_USE_STM32IMAGE */ 332 333 assert(bl_mem_params != NULL); 334 335 switch (image_id) { 336 #if !STM32MP_USE_STM32IMAGE 337 case FW_CONFIG_ID: 338 /* Set global DTB info for fixed fw_config information */ 339 set_config_info(STM32MP_FW_CONFIG_BASE, STM32MP_FW_CONFIG_MAX_SIZE, FW_CONFIG_ID); 340 fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE); 341 342 /* Iterate through all the fw config IDs */ 343 for (i = 0U; i < ARRAY_SIZE(image_ids); i++) { 344 bl_mem_params = get_bl_mem_params_node(image_ids[i]); 345 assert(bl_mem_params != NULL); 346 347 config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]); 348 if (config_info == NULL) { 349 continue; 350 } 351 352 bl_mem_params->image_info.image_base = config_info->config_addr; 353 bl_mem_params->image_info.image_max_size = config_info->config_max_size; 354 355 bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING; 356 357 switch (image_ids[i]) { 358 case BL32_IMAGE_ID: 359 bl_mem_params->ep_info.pc = config_info->config_addr; 360 361 /* In case of OPTEE, initialize address space with tos_fw addr */ 362 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 363 pager_mem_params->image_info.image_base = config_info->config_addr; 364 pager_mem_params->image_info.image_max_size = 365 config_info->config_max_size; 366 367 /* Init base and size for pager if exist */ 368 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 369 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 370 (dt_get_ddr_size() - STM32MP_DDR_S_SIZE - 371 STM32MP_DDR_SHMEM_SIZE); 372 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; 373 break; 374 375 case BL33_IMAGE_ID: 376 bl_mem_params->ep_info.pc = config_info->config_addr; 377 break; 378 379 case HW_CONFIG_ID: 380 case TOS_FW_CONFIG_ID: 381 break; 382 383 default: 384 return -EINVAL; 385 } 386 } 387 break; 388 #endif /* !STM32MP_USE_STM32IMAGE */ 389 390 case BL32_IMAGE_ID: 391 if (optee_header_is_valid(bl_mem_params->image_info.image_base)) { 392 /* BL32 is OP-TEE header */ 393 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 394 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 395 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 396 assert((pager_mem_params != NULL) && (paged_mem_params != NULL)); 397 398 #if STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) 399 /* Set OP-TEE extra image load areas at run-time */ 400 pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE; 401 pager_mem_params->image_info.image_max_size = STM32MP_OPTEE_SIZE; 402 403 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 404 dt_get_ddr_size() - 405 STM32MP_DDR_S_SIZE - 406 STM32MP_DDR_SHMEM_SIZE; 407 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; 408 #endif /* STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) */ 409 410 err = parse_optee_header(&bl_mem_params->ep_info, 411 &pager_mem_params->image_info, 412 &paged_mem_params->image_info); 413 if (err) { 414 ERROR("OPTEE header parse error.\n"); 415 panic(); 416 } 417 418 /* Set optee boot info from parsed header data */ 419 bl_mem_params->ep_info.args.arg0 = paged_mem_params->image_info.image_base; 420 bl_mem_params->ep_info.args.arg1 = 0; /* Unused */ 421 bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */ 422 } else { 423 #if !STM32MP_USE_STM32IMAGE 424 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 425 tos_fw_mem_params = get_bl_mem_params_node(TOS_FW_CONFIG_ID); 426 bl_mem_params->image_info.image_max_size += 427 tos_fw_mem_params->image_info.image_max_size; 428 #endif /* !STM32MP_USE_STM32IMAGE */ 429 bl_mem_params->ep_info.args.arg0 = 0; 430 } 431 break; 432 433 case BL33_IMAGE_ID: 434 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); 435 assert(bl32_mem_params != NULL); 436 bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; 437 break; 438 439 default: 440 /* Do nothing in default case */ 441 break; 442 } 443 444 #if STM32MP_SDMMC || STM32MP_EMMC 445 /* 446 * Invalidate remaining data read from MMC but not flushed by load_image_flush(). 447 * We take the worst case which is 2 MMC blocks. 448 */ 449 if ((image_id != FW_CONFIG_ID) && 450 ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) { 451 inv_dcache_range(bl_mem_params->image_info.image_base + 452 bl_mem_params->image_info.image_size, 453 2U * MMC_BLOCK_SIZE); 454 } 455 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 456 457 return err; 458 } 459 460 void bl2_el3_plat_prepare_exit(void) 461 { 462 uint16_t boot_itf = stm32mp_get_boot_itf_selected(); 463 464 switch (boot_itf) { 465 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 466 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART: 467 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 468 /* Invalidate the downloaded buffer used with io_memmap */ 469 inv_dcache_range(DWL_BUFFER_BASE, DWL_BUFFER_SIZE); 470 break; 471 #endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */ 472 default: 473 /* Do nothing in default case */ 474 break; 475 } 476 477 stm32mp1_security_setup(); 478 } 479