1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/desc_image_load.h> 15 #include <drivers/generic_delay_timer.h> 16 #include <drivers/mmc.h> 17 #include <drivers/st/bsec.h> 18 #include <drivers/st/regulator_fixed.h> 19 #include <drivers/st/stm32_iwdg.h> 20 #include <drivers/st/stm32_uart.h> 21 #include <drivers/st/stm32mp1_clk.h> 22 #include <drivers/st/stm32mp1_pwr.h> 23 #include <drivers/st/stm32mp1_ram.h> 24 #include <drivers/st/stm32mp_pmic.h> 25 #include <lib/fconf/fconf.h> 26 #include <lib/fconf/fconf_dyn_cfg_getter.h> 27 #include <lib/mmio.h> 28 #include <lib/optee_utils.h> 29 #include <lib/xlat_tables/xlat_tables_v2.h> 30 #include <plat/common/platform.h> 31 32 #include <platform_def.h> 33 #include <stm32mp1_dbgmcu.h> 34 35 static struct stm32mp_auth_ops stm32mp1_auth_ops; 36 37 static void print_reset_reason(void) 38 { 39 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR); 40 41 if (rstsr == 0U) { 42 WARN("Reset reason unknown\n"); 43 return; 44 } 45 46 INFO("Reset reason (0x%x):\n", rstsr); 47 48 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) { 49 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) { 50 INFO("System exits from STANDBY\n"); 51 return; 52 } 53 54 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) { 55 INFO("MPU exits from CSTANDBY\n"); 56 return; 57 } 58 } 59 60 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) { 61 INFO(" Power-on Reset (rst_por)\n"); 62 return; 63 } 64 65 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) { 66 INFO(" Brownout Reset (rst_bor)\n"); 67 return; 68 } 69 70 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) { 71 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 72 INFO(" System reset generated by MCU (MCSYSRST)\n"); 73 } else { 74 INFO(" Local reset generated by MCU (MCSYSRST)\n"); 75 } 76 return; 77 } 78 79 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) { 80 INFO(" System reset generated by MPU (MPSYSRST)\n"); 81 return; 82 } 83 84 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) { 85 INFO(" Reset due to a clock failure on HSE\n"); 86 return; 87 } 88 89 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) { 90 INFO(" IWDG1 Reset (rst_iwdg1)\n"); 91 return; 92 } 93 94 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) { 95 INFO(" IWDG2 Reset (rst_iwdg2)\n"); 96 return; 97 } 98 99 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) { 100 INFO(" MPU Processor 0 Reset\n"); 101 return; 102 } 103 104 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) { 105 INFO(" MPU Processor 1 Reset\n"); 106 return; 107 } 108 109 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 110 INFO(" Pad Reset from NRST\n"); 111 return; 112 } 113 114 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) { 115 INFO(" Reset due to a failure of VDD_CORE\n"); 116 return; 117 } 118 119 ERROR(" Unidentified reset reason\n"); 120 } 121 122 void bl2_el3_early_platform_setup(u_register_t arg0, 123 u_register_t arg1 __unused, 124 u_register_t arg2 __unused, 125 u_register_t arg3 __unused) 126 { 127 stm32mp_save_boot_ctx_address(arg0); 128 } 129 130 void bl2_platform_setup(void) 131 { 132 int ret; 133 134 ret = stm32mp1_ddr_probe(); 135 if (ret < 0) { 136 ERROR("Invalid DDR init: error %d\n", ret); 137 panic(); 138 } 139 140 /* Map DDR for binary load, now with cacheable attribute */ 141 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, 142 STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE); 143 if (ret < 0) { 144 ERROR("DDR mapping: error %d\n", ret); 145 panic(); 146 } 147 148 #if STM32MP_USE_STM32IMAGE 149 #ifdef AARCH32_SP_OPTEE 150 INFO("BL2 runs OP-TEE setup\n"); 151 #else 152 INFO("BL2 runs SP_MIN setup\n"); 153 #endif 154 #endif /* STM32MP_USE_STM32IMAGE */ 155 } 156 157 void bl2_el3_plat_arch_setup(void) 158 { 159 int32_t result; 160 const char *board_model; 161 boot_api_context_t *boot_context = 162 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 163 uintptr_t pwr_base; 164 uintptr_t rcc_base; 165 166 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 167 BL_CODE_END - BL_CODE_BASE, 168 MT_CODE | MT_SECURE); 169 170 #if STM32MP_USE_STM32IMAGE 171 #ifdef AARCH32_SP_OPTEE 172 mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE, 173 STM32MP_OPTEE_SIZE, 174 MT_MEMORY | MT_RW | MT_SECURE); 175 #else 176 /* Prevent corruption of preloaded BL32 */ 177 mmap_add_region(BL32_BASE, BL32_BASE, 178 BL32_LIMIT - BL32_BASE, 179 MT_RO_DATA | MT_SECURE); 180 #endif 181 #endif /* STM32MP_USE_STM32IMAGE */ 182 183 /* Prevent corruption of preloaded Device Tree */ 184 mmap_add_region(DTB_BASE, DTB_BASE, 185 DTB_LIMIT - DTB_BASE, 186 MT_RO_DATA | MT_SECURE); 187 188 configure_mmu(); 189 190 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) { 191 panic(); 192 } 193 194 pwr_base = stm32mp_pwr_base(); 195 rcc_base = stm32mp_rcc_base(); 196 197 /* 198 * Disable the backup domain write protection. 199 * The protection is enable at each reset by hardware 200 * and must be disabled by software. 201 */ 202 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP); 203 204 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) { 205 ; 206 } 207 208 if (bsec_probe() != 0) { 209 panic(); 210 } 211 212 /* Reset backup domain on cold boot cases */ 213 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 214 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 215 216 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 217 0U) { 218 ; 219 } 220 221 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 222 } 223 224 /* Disable MCKPROT */ 225 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); 226 227 generic_delay_timer_init(); 228 229 #if STM32MP_UART_PROGRAMMER 230 /* Disable programmer UART before changing clock tree */ 231 if (boot_context->boot_interface_selected == 232 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) { 233 uintptr_t uart_prog_addr = 234 get_uart_address(boot_context->boot_interface_instance); 235 236 stm32_uart_stop(uart_prog_addr); 237 } 238 #endif 239 if (stm32mp1_clk_probe() < 0) { 240 panic(); 241 } 242 243 if (stm32mp1_clk_init() < 0) { 244 panic(); 245 } 246 247 stm32_save_boot_interface(boot_context->boot_interface_selected, 248 boot_context->boot_interface_instance); 249 250 #if STM32MP_USB_PROGRAMMER 251 /* Deconfigure all UART RX pins configured by ROM code */ 252 stm32mp1_deconfigure_uart_pins(); 253 #endif 254 255 if (stm32mp_uart_console_setup() != 0) { 256 goto skip_console_init; 257 } 258 259 stm32mp_print_cpuinfo(); 260 261 board_model = dt_get_board_model(); 262 if (board_model != NULL) { 263 NOTICE("Model: %s\n", board_model); 264 } 265 266 stm32mp_print_boardinfo(); 267 268 if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) { 269 NOTICE("Bootrom authentication %s\n", 270 (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ? 271 "failed" : "succeeded"); 272 } 273 274 skip_console_init: 275 if (fixed_regulator_register() != 0) { 276 panic(); 277 } 278 279 if (dt_pmic_status() > 0) { 280 initialize_pmic(); 281 print_pmic_info_and_debug(); 282 } 283 284 stm32mp1_syscfg_init(); 285 286 if (stm32_iwdg_init() < 0) { 287 panic(); 288 } 289 290 stm32_iwdg_refresh(); 291 292 result = stm32mp1_dbgmcu_freeze_iwdg2(); 293 if (result != 0) { 294 INFO("IWDG2 freeze error : %i\n", result); 295 } 296 297 stm32mp1_auth_ops.check_key = boot_context->bootrom_ecdsa_check_key; 298 stm32mp1_auth_ops.verify_signature = 299 boot_context->bootrom_ecdsa_verify_signature; 300 301 stm32mp_init_auth(&stm32mp1_auth_ops); 302 303 stm32mp1_arch_security_setup(); 304 305 print_reset_reason(); 306 307 #if !STM32MP_USE_STM32IMAGE 308 fconf_populate("TB_FW", STM32MP_DTB_BASE); 309 #endif /* !STM32MP_USE_STM32IMAGE */ 310 311 stm32mp_io_setup(); 312 } 313 314 /******************************************************************************* 315 * This function can be used by the platforms to update/use image 316 * information for given `image_id`. 317 ******************************************************************************/ 318 int bl2_plat_handle_post_image_load(unsigned int image_id) 319 { 320 int err = 0; 321 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 322 bl_mem_params_node_t *bl32_mem_params; 323 bl_mem_params_node_t *pager_mem_params __unused; 324 bl_mem_params_node_t *paged_mem_params __unused; 325 #if !STM32MP_USE_STM32IMAGE 326 const struct dyn_cfg_dtb_info_t *config_info; 327 bl_mem_params_node_t *tos_fw_mem_params; 328 unsigned int i; 329 unsigned int idx; 330 unsigned long long ddr_top __unused; 331 const unsigned int image_ids[] = { 332 BL32_IMAGE_ID, 333 BL33_IMAGE_ID, 334 HW_CONFIG_ID, 335 TOS_FW_CONFIG_ID, 336 }; 337 #endif /* !STM32MP_USE_STM32IMAGE */ 338 339 assert(bl_mem_params != NULL); 340 341 switch (image_id) { 342 #if !STM32MP_USE_STM32IMAGE 343 case FW_CONFIG_ID: 344 /* Set global DTB info for fixed fw_config information */ 345 set_config_info(STM32MP_FW_CONFIG_BASE, STM32MP_FW_CONFIG_MAX_SIZE, FW_CONFIG_ID); 346 fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE); 347 348 idx = dyn_cfg_dtb_info_get_index(TOS_FW_CONFIG_ID); 349 350 /* Iterate through all the fw config IDs */ 351 for (i = 0U; i < ARRAY_SIZE(image_ids); i++) { 352 if ((image_ids[i] == TOS_FW_CONFIG_ID) && (idx == FCONF_INVALID_IDX)) { 353 continue; 354 } 355 356 bl_mem_params = get_bl_mem_params_node(image_ids[i]); 357 assert(bl_mem_params != NULL); 358 359 config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]); 360 if (config_info == NULL) { 361 continue; 362 } 363 364 bl_mem_params->image_info.image_base = config_info->config_addr; 365 bl_mem_params->image_info.image_max_size = config_info->config_max_size; 366 367 bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING; 368 369 switch (image_ids[i]) { 370 case BL32_IMAGE_ID: 371 bl_mem_params->ep_info.pc = config_info->config_addr; 372 373 /* In case of OPTEE, initialize address space with tos_fw addr */ 374 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 375 pager_mem_params->image_info.image_base = config_info->config_addr; 376 pager_mem_params->image_info.image_max_size = 377 config_info->config_max_size; 378 379 /* Init base and size for pager if exist */ 380 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 381 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 382 (dt_get_ddr_size() - STM32MP_DDR_S_SIZE - 383 STM32MP_DDR_SHMEM_SIZE); 384 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; 385 break; 386 387 case BL33_IMAGE_ID: 388 bl_mem_params->ep_info.pc = config_info->config_addr; 389 break; 390 391 case HW_CONFIG_ID: 392 case TOS_FW_CONFIG_ID: 393 break; 394 395 default: 396 return -EINVAL; 397 } 398 } 399 break; 400 #endif /* !STM32MP_USE_STM32IMAGE */ 401 402 case BL32_IMAGE_ID: 403 if (optee_header_is_valid(bl_mem_params->image_info.image_base)) { 404 /* BL32 is OP-TEE header */ 405 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 406 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 407 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 408 assert((pager_mem_params != NULL) && (paged_mem_params != NULL)); 409 410 #if STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) 411 /* Set OP-TEE extra image load areas at run-time */ 412 pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE; 413 pager_mem_params->image_info.image_max_size = STM32MP_OPTEE_SIZE; 414 415 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 416 dt_get_ddr_size() - 417 STM32MP_DDR_S_SIZE - 418 STM32MP_DDR_SHMEM_SIZE; 419 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; 420 #endif /* STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) */ 421 422 err = parse_optee_header(&bl_mem_params->ep_info, 423 &pager_mem_params->image_info, 424 &paged_mem_params->image_info); 425 if (err) { 426 ERROR("OPTEE header parse error.\n"); 427 panic(); 428 } 429 430 /* Set optee boot info from parsed header data */ 431 bl_mem_params->ep_info.args.arg0 = paged_mem_params->image_info.image_base; 432 bl_mem_params->ep_info.args.arg1 = 0; /* Unused */ 433 bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */ 434 } else { 435 #if !STM32MP_USE_STM32IMAGE 436 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 437 tos_fw_mem_params = get_bl_mem_params_node(TOS_FW_CONFIG_ID); 438 bl_mem_params->image_info.image_max_size += 439 tos_fw_mem_params->image_info.image_max_size; 440 #endif /* !STM32MP_USE_STM32IMAGE */ 441 bl_mem_params->ep_info.args.arg0 = 0; 442 } 443 break; 444 445 case BL33_IMAGE_ID: 446 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); 447 assert(bl32_mem_params != NULL); 448 bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; 449 break; 450 451 default: 452 /* Do nothing in default case */ 453 break; 454 } 455 456 #if STM32MP_SDMMC || STM32MP_EMMC 457 /* 458 * Invalidate remaining data read from MMC but not flushed by load_image_flush(). 459 * We take the worst case which is 2 MMC blocks. 460 */ 461 if ((image_id != FW_CONFIG_ID) && 462 ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) { 463 inv_dcache_range(bl_mem_params->image_info.image_base + 464 bl_mem_params->image_info.image_size, 465 2U * MMC_BLOCK_SIZE); 466 } 467 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 468 469 return err; 470 } 471 472 void bl2_el3_plat_prepare_exit(void) 473 { 474 uint16_t boot_itf = stm32mp_get_boot_itf_selected(); 475 476 switch (boot_itf) { 477 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 478 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART: 479 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 480 /* Invalidate the downloaded buffer used with io_memmap */ 481 inv_dcache_range(DWL_BUFFER_BASE, DWL_BUFFER_SIZE); 482 break; 483 #endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */ 484 default: 485 /* Do nothing in default case */ 486 break; 487 } 488 489 stm32mp1_security_setup(); 490 } 491