1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/desc_image_load.h> 15 #include <drivers/generic_delay_timer.h> 16 #include <drivers/mmc.h> 17 #include <drivers/st/bsec.h> 18 #include <drivers/st/regulator_fixed.h> 19 #include <drivers/st/stm32_iwdg.h> 20 #include <drivers/st/stm32_rng.h> 21 #include <drivers/st/stm32_uart.h> 22 #include <drivers/st/stm32mp1_clk.h> 23 #include <drivers/st/stm32mp1_pwr.h> 24 #include <drivers/st/stm32mp1_ram.h> 25 #include <drivers/st/stm32mp_pmic.h> 26 #include <lib/fconf/fconf.h> 27 #include <lib/fconf/fconf_dyn_cfg_getter.h> 28 #include <lib/mmio.h> 29 #include <lib/optee_utils.h> 30 #include <lib/xlat_tables/xlat_tables_v2.h> 31 #include <plat/common/platform.h> 32 33 #include <platform_def.h> 34 #include <stm32mp_common.h> 35 #include <stm32mp1_dbgmcu.h> 36 37 #if DEBUG 38 static const char debug_msg[] = { 39 "***************************************************\n" 40 "** DEBUG ACCESS PORT IS OPEN! **\n" 41 "** This boot image is only for debugging purpose **\n" 42 "** and is unsafe for production use. **\n" 43 "** **\n" 44 "** If you see this message and you are not **\n" 45 "** debugging report this immediately to your **\n" 46 "** vendor! **\n" 47 "***************************************************\n" 48 }; 49 #endif 50 51 static void print_reset_reason(void) 52 { 53 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR); 54 55 if (rstsr == 0U) { 56 WARN("Reset reason unknown\n"); 57 return; 58 } 59 60 INFO("Reset reason (0x%x):\n", rstsr); 61 62 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) { 63 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) { 64 INFO("System exits from STANDBY\n"); 65 return; 66 } 67 68 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) { 69 INFO("MPU exits from CSTANDBY\n"); 70 return; 71 } 72 } 73 74 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) { 75 INFO(" Power-on Reset (rst_por)\n"); 76 return; 77 } 78 79 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) { 80 INFO(" Brownout Reset (rst_bor)\n"); 81 return; 82 } 83 84 #if STM32MP15 85 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) { 86 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 87 INFO(" System reset generated by MCU (MCSYSRST)\n"); 88 } else { 89 INFO(" Local reset generated by MCU (MCSYSRST)\n"); 90 } 91 return; 92 } 93 #endif 94 95 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) { 96 INFO(" System reset generated by MPU (MPSYSRST)\n"); 97 return; 98 } 99 100 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) { 101 INFO(" Reset due to a clock failure on HSE\n"); 102 return; 103 } 104 105 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) { 106 INFO(" IWDG1 Reset (rst_iwdg1)\n"); 107 return; 108 } 109 110 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) { 111 INFO(" IWDG2 Reset (rst_iwdg2)\n"); 112 return; 113 } 114 115 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) { 116 INFO(" MPU Processor 0 Reset\n"); 117 return; 118 } 119 120 #if STM32MP15 121 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) { 122 INFO(" MPU Processor 1 Reset\n"); 123 return; 124 } 125 #endif 126 127 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 128 INFO(" Pad Reset from NRST\n"); 129 return; 130 } 131 132 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) { 133 INFO(" Reset due to a failure of VDD_CORE\n"); 134 return; 135 } 136 137 ERROR(" Unidentified reset reason\n"); 138 } 139 140 void bl2_el3_early_platform_setup(u_register_t arg0, 141 u_register_t arg1 __unused, 142 u_register_t arg2 __unused, 143 u_register_t arg3 __unused) 144 { 145 stm32mp_setup_early_console(); 146 147 stm32mp_save_boot_ctx_address(arg0); 148 } 149 150 void bl2_platform_setup(void) 151 { 152 int ret; 153 154 ret = stm32mp1_ddr_probe(); 155 if (ret < 0) { 156 ERROR("Invalid DDR init: error %d\n", ret); 157 panic(); 158 } 159 160 /* Map DDR for binary load, now with cacheable attribute */ 161 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, 162 STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE); 163 if (ret < 0) { 164 ERROR("DDR mapping: error %d\n", ret); 165 panic(); 166 } 167 168 #if STM32MP_USE_STM32IMAGE 169 #ifdef AARCH32_SP_OPTEE 170 INFO("BL2 runs OP-TEE setup\n"); 171 #else 172 INFO("BL2 runs SP_MIN setup\n"); 173 #endif 174 #endif /* STM32MP_USE_STM32IMAGE */ 175 } 176 177 #if STM32MP15 178 static void update_monotonic_counter(void) 179 { 180 uint32_t version; 181 uint32_t otp; 182 183 CASSERT(STM32_TF_VERSION <= MAX_MONOTONIC_VALUE, 184 assert_stm32mp1_monotonic_counter_reach_max); 185 186 /* Check if monotonic counter needs to be incremented */ 187 if (stm32_get_otp_index(MONOTONIC_OTP, &otp, NULL) != 0) { 188 panic(); 189 } 190 191 if (stm32_get_otp_value_from_idx(otp, &version) != 0) { 192 panic(); 193 } 194 195 if ((version + 1U) < BIT(STM32_TF_VERSION)) { 196 uint32_t result; 197 198 /* Need to increment the monotonic counter. */ 199 version = BIT(STM32_TF_VERSION) - 1U; 200 201 result = bsec_program_otp(version, otp); 202 if (result != BSEC_OK) { 203 ERROR("BSEC: MONOTONIC_OTP program Error %u\n", 204 result); 205 panic(); 206 } 207 INFO("Monotonic counter has been incremented (value 0x%x)\n", 208 version); 209 } 210 } 211 #endif 212 213 void bl2_el3_plat_arch_setup(void) 214 { 215 const char *board_model; 216 boot_api_context_t *boot_context = 217 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 218 uintptr_t pwr_base; 219 uintptr_t rcc_base; 220 221 if (bsec_probe() != 0U) { 222 panic(); 223 } 224 225 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 226 BL_CODE_END - BL_CODE_BASE, 227 MT_CODE | MT_SECURE); 228 229 #if STM32MP_USE_STM32IMAGE 230 #ifdef AARCH32_SP_OPTEE 231 mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE, 232 STM32MP_OPTEE_SIZE, 233 MT_MEMORY | MT_RW | MT_SECURE); 234 #else 235 /* Prevent corruption of preloaded BL32 */ 236 mmap_add_region(BL32_BASE, BL32_BASE, 237 BL32_LIMIT - BL32_BASE, 238 MT_RO_DATA | MT_SECURE); 239 #endif 240 #endif /* STM32MP_USE_STM32IMAGE */ 241 242 /* Prevent corruption of preloaded Device Tree */ 243 mmap_add_region(DTB_BASE, DTB_BASE, 244 DTB_LIMIT - DTB_BASE, 245 MT_RO_DATA | MT_SECURE); 246 247 configure_mmu(); 248 249 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) { 250 panic(); 251 } 252 253 pwr_base = stm32mp_pwr_base(); 254 rcc_base = stm32mp_rcc_base(); 255 256 /* 257 * Disable the backup domain write protection. 258 * The protection is enable at each reset by hardware 259 * and must be disabled by software. 260 */ 261 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP); 262 263 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) { 264 ; 265 } 266 267 /* Reset backup domain on cold boot cases */ 268 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 269 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 270 271 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 272 0U) { 273 ; 274 } 275 276 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 277 } 278 279 #if STM32MP15 280 /* Disable MCKPROT */ 281 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); 282 #endif 283 284 /* 285 * Set minimum reset pulse duration to 31ms for discrete power 286 * supplied boards. 287 */ 288 if (dt_pmic_status() <= 0) { 289 mmio_clrsetbits_32(rcc_base + RCC_RDLSICR, 290 RCC_RDLSICR_MRD_MASK, 291 31U << RCC_RDLSICR_MRD_SHIFT); 292 } 293 294 generic_delay_timer_init(); 295 296 #if STM32MP_UART_PROGRAMMER 297 /* Disable programmer UART before changing clock tree */ 298 if (boot_context->boot_interface_selected == 299 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) { 300 uintptr_t uart_prog_addr = 301 get_uart_address(boot_context->boot_interface_instance); 302 303 stm32_uart_stop(uart_prog_addr); 304 } 305 #endif 306 if (stm32mp1_clk_probe() < 0) { 307 panic(); 308 } 309 310 if (stm32mp1_clk_init() < 0) { 311 panic(); 312 } 313 314 stm32_save_boot_interface(boot_context->boot_interface_selected, 315 boot_context->boot_interface_instance); 316 stm32_save_boot_auth(boot_context->auth_status, 317 boot_context->boot_partition_used_toboot); 318 319 #if STM32MP_USB_PROGRAMMER && STM32MP15 320 /* Deconfigure all UART RX pins configured by ROM code */ 321 stm32mp1_deconfigure_uart_pins(); 322 #endif 323 324 if (stm32mp_uart_console_setup() != 0) { 325 goto skip_console_init; 326 } 327 328 stm32mp_print_cpuinfo(); 329 330 board_model = dt_get_board_model(); 331 if (board_model != NULL) { 332 NOTICE("Model: %s\n", board_model); 333 } 334 335 stm32mp_print_boardinfo(); 336 337 if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) { 338 NOTICE("Bootrom authentication %s\n", 339 (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ? 340 "failed" : "succeeded"); 341 } 342 343 skip_console_init: 344 if (fixed_regulator_register() != 0) { 345 panic(); 346 } 347 348 if (dt_pmic_status() > 0) { 349 initialize_pmic(); 350 if (pmic_voltages_init() != 0) { 351 ERROR("PMIC voltages init failed\n"); 352 panic(); 353 } 354 print_pmic_info_and_debug(); 355 } 356 357 stm32mp1_syscfg_init(); 358 359 if (stm32_iwdg_init() < 0) { 360 panic(); 361 } 362 363 stm32_iwdg_refresh(); 364 365 if (bsec_read_debug_conf() != 0U) { 366 if (stm32mp_is_closed_device()) { 367 #if DEBUG 368 WARN("\n%s", debug_msg); 369 #else 370 ERROR("***Debug opened on closed chip***\n"); 371 #endif 372 } 373 } 374 375 #if STM32MP13 376 if (stm32_rng_init() != 0) { 377 panic(); 378 } 379 #endif 380 381 stm32mp1_arch_security_setup(); 382 383 print_reset_reason(); 384 385 #if STM32MP15 386 update_monotonic_counter(); 387 #endif 388 389 stm32mp1_syscfg_enable_io_compensation_finish(); 390 391 #if !STM32MP_USE_STM32IMAGE 392 fconf_populate("TB_FW", STM32MP_DTB_BASE); 393 #endif /* !STM32MP_USE_STM32IMAGE */ 394 395 stm32mp_io_setup(); 396 } 397 398 /******************************************************************************* 399 * This function can be used by the platforms to update/use image 400 * information for given `image_id`. 401 ******************************************************************************/ 402 int bl2_plat_handle_post_image_load(unsigned int image_id) 403 { 404 int err = 0; 405 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 406 bl_mem_params_node_t *bl32_mem_params; 407 bl_mem_params_node_t *pager_mem_params __unused; 408 bl_mem_params_node_t *paged_mem_params __unused; 409 #if !STM32MP_USE_STM32IMAGE 410 const struct dyn_cfg_dtb_info_t *config_info; 411 bl_mem_params_node_t *tos_fw_mem_params; 412 unsigned int i; 413 unsigned int idx; 414 unsigned long long ddr_top __unused; 415 const unsigned int image_ids[] = { 416 BL32_IMAGE_ID, 417 BL33_IMAGE_ID, 418 HW_CONFIG_ID, 419 TOS_FW_CONFIG_ID, 420 }; 421 #endif /* !STM32MP_USE_STM32IMAGE */ 422 423 assert(bl_mem_params != NULL); 424 425 switch (image_id) { 426 #if !STM32MP_USE_STM32IMAGE 427 case FW_CONFIG_ID: 428 /* Set global DTB info for fixed fw_config information */ 429 set_config_info(STM32MP_FW_CONFIG_BASE, ~0UL, STM32MP_FW_CONFIG_MAX_SIZE, 430 FW_CONFIG_ID); 431 fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE); 432 433 idx = dyn_cfg_dtb_info_get_index(TOS_FW_CONFIG_ID); 434 435 /* Iterate through all the fw config IDs */ 436 for (i = 0U; i < ARRAY_SIZE(image_ids); i++) { 437 if ((image_ids[i] == TOS_FW_CONFIG_ID) && (idx == FCONF_INVALID_IDX)) { 438 continue; 439 } 440 441 bl_mem_params = get_bl_mem_params_node(image_ids[i]); 442 assert(bl_mem_params != NULL); 443 444 config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]); 445 if (config_info == NULL) { 446 continue; 447 } 448 449 bl_mem_params->image_info.image_base = config_info->config_addr; 450 bl_mem_params->image_info.image_max_size = config_info->config_max_size; 451 452 bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING; 453 454 switch (image_ids[i]) { 455 case BL32_IMAGE_ID: 456 bl_mem_params->ep_info.pc = config_info->config_addr; 457 458 /* In case of OPTEE, initialize address space with tos_fw addr */ 459 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 460 assert(pager_mem_params != NULL); 461 pager_mem_params->image_info.image_base = config_info->config_addr; 462 pager_mem_params->image_info.image_max_size = 463 config_info->config_max_size; 464 465 /* Init base and size for pager if exist */ 466 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 467 if (paged_mem_params != NULL) { 468 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 469 (dt_get_ddr_size() - STM32MP_DDR_S_SIZE - 470 STM32MP_DDR_SHMEM_SIZE); 471 paged_mem_params->image_info.image_max_size = 472 STM32MP_DDR_S_SIZE; 473 } 474 break; 475 476 case BL33_IMAGE_ID: 477 bl_mem_params->ep_info.pc = config_info->config_addr; 478 break; 479 480 case HW_CONFIG_ID: 481 case TOS_FW_CONFIG_ID: 482 break; 483 484 default: 485 return -EINVAL; 486 } 487 } 488 break; 489 #endif /* !STM32MP_USE_STM32IMAGE */ 490 491 case BL32_IMAGE_ID: 492 if (optee_header_is_valid(bl_mem_params->image_info.image_base)) { 493 image_info_t *paged_image_info = NULL; 494 495 /* BL32 is OP-TEE header */ 496 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 497 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 498 assert(pager_mem_params != NULL); 499 500 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 501 if (paged_mem_params != NULL) { 502 paged_image_info = &paged_mem_params->image_info; 503 } 504 505 #if STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) 506 /* Set OP-TEE extra image load areas at run-time */ 507 pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE; 508 pager_mem_params->image_info.image_max_size = STM32MP_OPTEE_SIZE; 509 510 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 511 dt_get_ddr_size() - 512 STM32MP_DDR_S_SIZE - 513 STM32MP_DDR_SHMEM_SIZE; 514 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; 515 #endif /* STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) */ 516 517 err = parse_optee_header(&bl_mem_params->ep_info, 518 &pager_mem_params->image_info, 519 paged_image_info); 520 if (err != 0) { 521 ERROR("OPTEE header parse error.\n"); 522 panic(); 523 } 524 525 /* Set optee boot info from parsed header data */ 526 if (paged_mem_params != NULL) { 527 bl_mem_params->ep_info.args.arg0 = 528 paged_mem_params->image_info.image_base; 529 } else { 530 bl_mem_params->ep_info.args.arg0 = 0U; 531 } 532 533 bl_mem_params->ep_info.args.arg1 = 0U; /* Unused */ 534 bl_mem_params->ep_info.args.arg2 = 0U; /* No DT supported */ 535 } else { 536 #if !STM32MP_USE_STM32IMAGE 537 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 538 tos_fw_mem_params = get_bl_mem_params_node(TOS_FW_CONFIG_ID); 539 assert(tos_fw_mem_params != NULL); 540 bl_mem_params->image_info.image_max_size += 541 tos_fw_mem_params->image_info.image_max_size; 542 #endif /* !STM32MP_USE_STM32IMAGE */ 543 bl_mem_params->ep_info.args.arg0 = 0; 544 } 545 break; 546 547 case BL33_IMAGE_ID: 548 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); 549 assert(bl32_mem_params != NULL); 550 bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; 551 #if !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT 552 stm32mp1_fwu_set_boot_idx(); 553 #endif /* !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT */ 554 break; 555 556 default: 557 /* Do nothing in default case */ 558 break; 559 } 560 561 #if STM32MP_SDMMC || STM32MP_EMMC 562 /* 563 * Invalidate remaining data read from MMC but not flushed by load_image_flush(). 564 * We take the worst case which is 2 MMC blocks. 565 */ 566 if ((image_id != FW_CONFIG_ID) && 567 ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) { 568 inv_dcache_range(bl_mem_params->image_info.image_base + 569 bl_mem_params->image_info.image_size, 570 2U * MMC_BLOCK_SIZE); 571 } 572 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 573 574 return err; 575 } 576 577 void bl2_el3_plat_prepare_exit(void) 578 { 579 uint16_t boot_itf = stm32mp_get_boot_itf_selected(); 580 581 switch (boot_itf) { 582 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 583 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART: 584 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 585 /* Invalidate the downloaded buffer used with io_memmap */ 586 inv_dcache_range(DWL_BUFFER_BASE, DWL_BUFFER_SIZE); 587 break; 588 #endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */ 589 default: 590 /* Do nothing in default case */ 591 break; 592 } 593 594 stm32mp1_security_setup(); 595 } 596