1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/desc_image_load.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/mmc.h> 19 #include <drivers/st/bsec.h> 20 #include <drivers/st/stm32_iwdg.h> 21 #include <drivers/st/stm32mp_pmic.h> 22 #include <drivers/st/stm32mp1_clk.h> 23 #include <drivers/st/stm32mp1_pwr.h> 24 #include <drivers/st/stm32mp1_ram.h> 25 #include <lib/fconf/fconf.h> 26 #include <lib/fconf/fconf_dyn_cfg_getter.h> 27 #include <lib/mmio.h> 28 #include <lib/optee_utils.h> 29 #include <lib/xlat_tables/xlat_tables_v2.h> 30 #include <plat/common/platform.h> 31 32 #include <stm32mp1_dbgmcu.h> 33 34 static struct stm32mp_auth_ops stm32mp1_auth_ops; 35 36 static void print_reset_reason(void) 37 { 38 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR); 39 40 if (rstsr == 0U) { 41 WARN("Reset reason unknown\n"); 42 return; 43 } 44 45 INFO("Reset reason (0x%x):\n", rstsr); 46 47 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) { 48 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) { 49 INFO("System exits from STANDBY\n"); 50 return; 51 } 52 53 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) { 54 INFO("MPU exits from CSTANDBY\n"); 55 return; 56 } 57 } 58 59 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) { 60 INFO(" Power-on Reset (rst_por)\n"); 61 return; 62 } 63 64 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) { 65 INFO(" Brownout Reset (rst_bor)\n"); 66 return; 67 } 68 69 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) { 70 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 71 INFO(" System reset generated by MCU (MCSYSRST)\n"); 72 } else { 73 INFO(" Local reset generated by MCU (MCSYSRST)\n"); 74 } 75 return; 76 } 77 78 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) { 79 INFO(" System reset generated by MPU (MPSYSRST)\n"); 80 return; 81 } 82 83 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) { 84 INFO(" Reset due to a clock failure on HSE\n"); 85 return; 86 } 87 88 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) { 89 INFO(" IWDG1 Reset (rst_iwdg1)\n"); 90 return; 91 } 92 93 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) { 94 INFO(" IWDG2 Reset (rst_iwdg2)\n"); 95 return; 96 } 97 98 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) { 99 INFO(" MPU Processor 0 Reset\n"); 100 return; 101 } 102 103 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) { 104 INFO(" MPU Processor 1 Reset\n"); 105 return; 106 } 107 108 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 109 INFO(" Pad Reset from NRST\n"); 110 return; 111 } 112 113 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) { 114 INFO(" Reset due to a failure of VDD_CORE\n"); 115 return; 116 } 117 118 ERROR(" Unidentified reset reason\n"); 119 } 120 121 void bl2_el3_early_platform_setup(u_register_t arg0, 122 u_register_t arg1 __unused, 123 u_register_t arg2 __unused, 124 u_register_t arg3 __unused) 125 { 126 stm32mp_save_boot_ctx_address(arg0); 127 } 128 129 void bl2_platform_setup(void) 130 { 131 int ret; 132 133 if (dt_pmic_status() > 0) { 134 initialize_pmic(); 135 } 136 137 ret = stm32mp1_ddr_probe(); 138 if (ret < 0) { 139 ERROR("Invalid DDR init: error %d\n", ret); 140 panic(); 141 } 142 143 /* Map DDR for binary load, now with cacheable attribute */ 144 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, 145 STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE); 146 if (ret < 0) { 147 ERROR("DDR mapping: error %d\n", ret); 148 panic(); 149 } 150 151 #if STM32MP_USE_STM32IMAGE 152 #ifdef AARCH32_SP_OPTEE 153 INFO("BL2 runs OP-TEE setup\n"); 154 #else 155 INFO("BL2 runs SP_MIN setup\n"); 156 #endif 157 #endif /* STM32MP_USE_STM32IMAGE */ 158 } 159 160 void bl2_el3_plat_arch_setup(void) 161 { 162 int32_t result; 163 const char *board_model; 164 boot_api_context_t *boot_context = 165 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 166 uintptr_t pwr_base; 167 uintptr_t rcc_base; 168 169 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 170 BL_CODE_END - BL_CODE_BASE, 171 MT_CODE | MT_SECURE); 172 173 #if STM32MP_USE_STM32IMAGE 174 #ifdef AARCH32_SP_OPTEE 175 mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE, 176 STM32MP_OPTEE_SIZE, 177 MT_MEMORY | MT_RW | MT_SECURE); 178 #else 179 /* Prevent corruption of preloaded BL32 */ 180 mmap_add_region(BL32_BASE, BL32_BASE, 181 BL32_LIMIT - BL32_BASE, 182 MT_RO_DATA | MT_SECURE); 183 #endif 184 #endif /* STM32MP_USE_STM32IMAGE */ 185 186 /* Prevent corruption of preloaded Device Tree */ 187 mmap_add_region(DTB_BASE, DTB_BASE, 188 DTB_LIMIT - DTB_BASE, 189 MT_RO_DATA | MT_SECURE); 190 191 configure_mmu(); 192 193 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) { 194 panic(); 195 } 196 197 pwr_base = stm32mp_pwr_base(); 198 rcc_base = stm32mp_rcc_base(); 199 200 /* 201 * Disable the backup domain write protection. 202 * The protection is enable at each reset by hardware 203 * and must be disabled by software. 204 */ 205 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP); 206 207 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) { 208 ; 209 } 210 211 if (bsec_probe() != 0) { 212 panic(); 213 } 214 215 /* Reset backup domain on cold boot cases */ 216 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 217 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 218 219 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 220 0U) { 221 ; 222 } 223 224 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 225 } 226 227 /* Disable MCKPROT */ 228 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); 229 230 generic_delay_timer_init(); 231 232 if (stm32mp1_clk_probe() < 0) { 233 panic(); 234 } 235 236 if (stm32mp1_clk_init() < 0) { 237 panic(); 238 } 239 240 stm32mp1_syscfg_init(); 241 242 stm32_save_boot_interface(boot_context->boot_interface_selected, 243 boot_context->boot_interface_instance); 244 245 #if STM32MP_USB_PROGRAMMER 246 /* Deconfigure all UART RX pins configured by ROM code */ 247 stm32mp1_deconfigure_uart_pins(); 248 #endif 249 250 if (stm32mp_uart_console_setup() != 0) { 251 goto skip_console_init; 252 } 253 254 stm32mp_print_cpuinfo(); 255 256 board_model = dt_get_board_model(); 257 if (board_model != NULL) { 258 NOTICE("Model: %s\n", board_model); 259 } 260 261 stm32mp_print_boardinfo(); 262 263 if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) { 264 NOTICE("Bootrom authentication %s\n", 265 (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ? 266 "failed" : "succeeded"); 267 } 268 269 skip_console_init: 270 if (stm32_iwdg_init() < 0) { 271 panic(); 272 } 273 274 stm32_iwdg_refresh(); 275 276 result = stm32mp1_dbgmcu_freeze_iwdg2(); 277 if (result != 0) { 278 INFO("IWDG2 freeze error : %i\n", result); 279 } 280 281 stm32mp1_auth_ops.check_key = boot_context->bootrom_ecdsa_check_key; 282 stm32mp1_auth_ops.verify_signature = 283 boot_context->bootrom_ecdsa_verify_signature; 284 285 stm32mp_init_auth(&stm32mp1_auth_ops); 286 287 stm32mp1_arch_security_setup(); 288 289 print_reset_reason(); 290 291 #if !STM32MP_USE_STM32IMAGE 292 fconf_populate("TB_FW", STM32MP_DTB_BASE); 293 #endif /* !STM32MP_USE_STM32IMAGE */ 294 295 stm32mp_io_setup(); 296 } 297 298 /******************************************************************************* 299 * This function can be used by the platforms to update/use image 300 * information for given `image_id`. 301 ******************************************************************************/ 302 int bl2_plat_handle_post_image_load(unsigned int image_id) 303 { 304 int err = 0; 305 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 306 bl_mem_params_node_t *bl32_mem_params; 307 bl_mem_params_node_t *pager_mem_params __unused; 308 bl_mem_params_node_t *paged_mem_params __unused; 309 #if !STM32MP_USE_STM32IMAGE 310 const struct dyn_cfg_dtb_info_t *config_info; 311 bl_mem_params_node_t *tos_fw_mem_params; 312 unsigned int i; 313 unsigned long long ddr_top __unused; 314 const unsigned int image_ids[] = { 315 BL32_IMAGE_ID, 316 BL33_IMAGE_ID, 317 HW_CONFIG_ID, 318 TOS_FW_CONFIG_ID, 319 }; 320 #endif /* !STM32MP_USE_STM32IMAGE */ 321 322 assert(bl_mem_params != NULL); 323 324 switch (image_id) { 325 #if !STM32MP_USE_STM32IMAGE 326 case FW_CONFIG_ID: 327 /* Set global DTB info for fixed fw_config information */ 328 set_config_info(STM32MP_FW_CONFIG_BASE, STM32MP_FW_CONFIG_MAX_SIZE, FW_CONFIG_ID); 329 fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE); 330 331 /* Iterate through all the fw config IDs */ 332 for (i = 0U; i < ARRAY_SIZE(image_ids); i++) { 333 bl_mem_params = get_bl_mem_params_node(image_ids[i]); 334 assert(bl_mem_params != NULL); 335 336 config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]); 337 if (config_info == NULL) { 338 continue; 339 } 340 341 bl_mem_params->image_info.image_base = config_info->config_addr; 342 bl_mem_params->image_info.image_max_size = config_info->config_max_size; 343 344 bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING; 345 346 switch (image_ids[i]) { 347 case BL32_IMAGE_ID: 348 bl_mem_params->ep_info.pc = config_info->config_addr; 349 350 /* In case of OPTEE, initialize address space with tos_fw addr */ 351 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 352 pager_mem_params->image_info.image_base = config_info->config_addr; 353 pager_mem_params->image_info.image_max_size = 354 config_info->config_max_size; 355 356 /* Init base and size for pager if exist */ 357 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 358 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 359 (dt_get_ddr_size() - STM32MP_DDR_S_SIZE - 360 STM32MP_DDR_SHMEM_SIZE); 361 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; 362 break; 363 364 case BL33_IMAGE_ID: 365 bl_mem_params->ep_info.pc = config_info->config_addr; 366 break; 367 368 case HW_CONFIG_ID: 369 case TOS_FW_CONFIG_ID: 370 break; 371 372 default: 373 return -EINVAL; 374 } 375 } 376 break; 377 #endif /* !STM32MP_USE_STM32IMAGE */ 378 379 case BL32_IMAGE_ID: 380 if (optee_header_is_valid(bl_mem_params->image_info.image_base)) { 381 /* BL32 is OP-TEE header */ 382 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 383 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 384 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 385 assert((pager_mem_params != NULL) && (paged_mem_params != NULL)); 386 387 #if STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) 388 /* Set OP-TEE extra image load areas at run-time */ 389 pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE; 390 pager_mem_params->image_info.image_max_size = STM32MP_OPTEE_SIZE; 391 392 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 393 dt_get_ddr_size() - 394 STM32MP_DDR_S_SIZE - 395 STM32MP_DDR_SHMEM_SIZE; 396 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; 397 #endif /* STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) */ 398 399 err = parse_optee_header(&bl_mem_params->ep_info, 400 &pager_mem_params->image_info, 401 &paged_mem_params->image_info); 402 if (err) { 403 ERROR("OPTEE header parse error.\n"); 404 panic(); 405 } 406 407 /* Set optee boot info from parsed header data */ 408 bl_mem_params->ep_info.args.arg0 = paged_mem_params->image_info.image_base; 409 bl_mem_params->ep_info.args.arg1 = 0; /* Unused */ 410 bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */ 411 } else { 412 #if !STM32MP_USE_STM32IMAGE 413 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 414 tos_fw_mem_params = get_bl_mem_params_node(TOS_FW_CONFIG_ID); 415 bl_mem_params->image_info.image_max_size += 416 tos_fw_mem_params->image_info.image_max_size; 417 #endif /* !STM32MP_USE_STM32IMAGE */ 418 bl_mem_params->ep_info.args.arg0 = 0; 419 } 420 break; 421 422 case BL33_IMAGE_ID: 423 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); 424 assert(bl32_mem_params != NULL); 425 bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; 426 break; 427 428 default: 429 /* Do nothing in default case */ 430 break; 431 } 432 433 #if STM32MP_SDMMC || STM32MP_EMMC 434 /* 435 * Invalidate remaining data read from MMC but not flushed by load_image_flush(). 436 * We take the worst case which is 2 MMC blocks. 437 */ 438 if ((image_id != FW_CONFIG_ID) && 439 ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) { 440 inv_dcache_range(bl_mem_params->image_info.image_base + 441 bl_mem_params->image_info.image_size, 442 2U * MMC_BLOCK_SIZE); 443 } 444 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 445 446 return err; 447 } 448 449 void bl2_el3_plat_prepare_exit(void) 450 { 451 uint16_t boot_itf = stm32mp_get_boot_itf_selected(); 452 453 switch (boot_itf) { 454 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 455 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART: 456 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 457 /* Invalidate the downloaded buffer used with io_memmap */ 458 inv_dcache_range(DWL_BUFFER_BASE, DWL_BUFFER_SIZE); 459 break; 460 #endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */ 461 default: 462 /* Do nothing in default case */ 463 break; 464 } 465 466 stm32mp1_security_setup(); 467 } 468