1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/desc_image_load.h> 16 #include <drivers/delay_timer.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/st/stm32_console.h> 19 #include <drivers/st/stm32mp_pmic.h> 20 #include <drivers/st/stm32mp1_clk.h> 21 #include <drivers/st/stm32mp1_pwr.h> 22 #include <drivers/st/stm32mp1_ram.h> 23 #include <drivers/st/stm32mp1_rcc.h> 24 #include <drivers/st/stm32mp1_reset.h> 25 #include <lib/mmio.h> 26 #include <lib/xlat_tables/xlat_tables_v2.h> 27 #include <plat/common/platform.h> 28 29 #include <boot_api.h> 30 #include <stm32mp1_context.h> 31 #include <stm32mp1_dt.h> 32 #include <stm32mp1_private.h> 33 34 static struct console_stm32 console; 35 36 static void print_reset_reason(void) 37 { 38 uint32_t rstsr = mmio_read_32(RCC_BASE + RCC_MP_RSTSCLRR); 39 40 if (rstsr == 0U) { 41 WARN("Reset reason unknown\n"); 42 return; 43 } 44 45 INFO("Reset reason (0x%x):\n", rstsr); 46 47 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) { 48 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) { 49 INFO("System exits from STANDBY\n"); 50 return; 51 } 52 53 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) { 54 INFO("MPU exits from CSTANDBY\n"); 55 return; 56 } 57 } 58 59 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) { 60 INFO(" Power-on Reset (rst_por)\n"); 61 return; 62 } 63 64 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) { 65 INFO(" Brownout Reset (rst_bor)\n"); 66 return; 67 } 68 69 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) { 70 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 71 INFO(" System reset generated by MCU (MCSYSRST)\n"); 72 } else { 73 INFO(" Local reset generated by MCU (MCSYSRST)\n"); 74 } 75 return; 76 } 77 78 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) { 79 INFO(" System reset generated by MPU (MPSYSRST)\n"); 80 return; 81 } 82 83 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) { 84 INFO(" Reset due to a clock failure on HSE\n"); 85 return; 86 } 87 88 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) { 89 INFO(" IWDG1 Reset (rst_iwdg1)\n"); 90 return; 91 } 92 93 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) { 94 INFO(" IWDG2 Reset (rst_iwdg2)\n"); 95 return; 96 } 97 98 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) { 99 INFO(" MPU Processor 0 Reset\n"); 100 return; 101 } 102 103 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) { 104 INFO(" MPU Processor 1 Reset\n"); 105 return; 106 } 107 108 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 109 INFO(" Pad Reset from NRST\n"); 110 return; 111 } 112 113 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) { 114 INFO(" Reset due to a failure of VDD_CORE\n"); 115 return; 116 } 117 118 ERROR(" Unidentified reset reason\n"); 119 } 120 121 void bl2_el3_early_platform_setup(u_register_t arg0, 122 u_register_t arg1 __unused, 123 u_register_t arg2 __unused, 124 u_register_t arg3 __unused) 125 { 126 stm32mp1_save_boot_ctx_address(arg0); 127 } 128 129 void bl2_platform_setup(void) 130 { 131 int ret; 132 133 if (dt_check_pmic()) { 134 initialize_pmic(); 135 } 136 137 ret = stm32mp1_ddr_probe(); 138 if (ret < 0) { 139 ERROR("Invalid DDR init: error %d\n", ret); 140 panic(); 141 } 142 143 INFO("BL2 runs SP_MIN setup\n"); 144 } 145 146 void bl2_el3_plat_arch_setup(void) 147 { 148 int32_t result; 149 struct dt_node_info dt_uart_info; 150 const char *board_model; 151 boot_api_context_t *boot_context = 152 (boot_api_context_t *)stm32mp1_get_boot_ctx_address(); 153 uint32_t clk_rate; 154 155 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 156 BL_CODE_END - BL_CODE_BASE, 157 MT_CODE | MT_SECURE); 158 159 /* Prevent corruption of preloaded BL32 */ 160 mmap_add_region(BL32_BASE, BL32_BASE, 161 BL32_LIMIT - BL32_BASE, 162 MT_MEMORY | MT_RO | MT_SECURE); 163 164 /* Map non secure DDR for BL33 load and DDR training area restore */ 165 mmap_add_region(STM32MP1_DDR_BASE, 166 STM32MP1_DDR_BASE, 167 STM32MP1_DDR_MAX_SIZE, 168 MT_MEMORY | MT_RW | MT_NS); 169 170 /* Prevent corruption of preloaded Device Tree */ 171 mmap_add_region(DTB_BASE, DTB_BASE, 172 DTB_LIMIT - DTB_BASE, 173 MT_MEMORY | MT_RO | MT_SECURE); 174 175 configure_mmu(); 176 177 if (dt_open_and_check() < 0) { 178 panic(); 179 } 180 181 /* 182 * Disable the backup domain write protection. 183 * The protection is enable at each reset by hardware 184 * and must be disabled by software. 185 */ 186 mmio_setbits_32(PWR_BASE + PWR_CR1, PWR_CR1_DBP); 187 188 while ((mmio_read_32(PWR_BASE + PWR_CR1) & PWR_CR1_DBP) == 0U) { 189 ; 190 } 191 192 /* Reset backup domain on cold boot cases */ 193 if ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 194 mmio_setbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); 195 196 while ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_VSWRST) == 197 0U) { 198 ; 199 } 200 201 mmio_clrbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); 202 } 203 204 generic_delay_timer_init(); 205 206 if (stm32mp1_clk_probe() < 0) { 207 panic(); 208 } 209 210 if (stm32mp1_clk_init() < 0) { 211 panic(); 212 } 213 214 result = dt_get_stdout_uart_info(&dt_uart_info); 215 216 if ((result <= 0) || 217 (dt_uart_info.status == 0U) || 218 (dt_uart_info.clock < 0) || 219 (dt_uart_info.reset < 0)) { 220 goto skip_console_init; 221 } 222 223 if (dt_set_stdout_pinctrl() != 0) { 224 goto skip_console_init; 225 } 226 227 if (stm32mp1_clk_enable((unsigned long)dt_uart_info.clock) != 0) { 228 goto skip_console_init; 229 } 230 231 stm32mp1_reset_assert((uint32_t)dt_uart_info.reset); 232 udelay(2); 233 stm32mp1_reset_deassert((uint32_t)dt_uart_info.reset); 234 mdelay(1); 235 236 clk_rate = stm32mp1_clk_get_rate((unsigned long)dt_uart_info.clock); 237 238 if (console_stm32_register(dt_uart_info.base, clk_rate, 239 STM32MP1_UART_BAUDRATE, &console) == 0) { 240 panic(); 241 } 242 243 board_model = dt_get_board_model(); 244 if (board_model != NULL) { 245 NOTICE("Model: %s\n", board_model); 246 } 247 248 skip_console_init: 249 250 if (stm32_save_boot_interface(boot_context->boot_interface_selected, 251 boot_context->boot_interface_instance) != 252 0) { 253 ERROR("Cannot save boot interface\n"); 254 } 255 256 stm32mp1_arch_security_setup(); 257 258 print_reset_reason(); 259 260 stm32mp1_io_setup(); 261 } 262