1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <boot_api.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <delay_timer.h> 14 #include <desc_image_load.h> 15 #include <generic_delay_timer.h> 16 #include <mmio.h> 17 #include <platform.h> 18 #include <platform_def.h> 19 #include <stm32mp1_clk.h> 20 #include <stm32mp1_dt.h> 21 #include <stm32mp1_pmic.h> 22 #include <stm32mp1_private.h> 23 #include <stm32mp1_context.h> 24 #include <stm32mp1_pwr.h> 25 #include <stm32mp1_ram.h> 26 #include <stm32mp1_rcc.h> 27 #include <stm32mp1_reset.h> 28 #include <string.h> 29 #include <xlat_tables_v2.h> 30 31 void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1, 32 u_register_t arg2, u_register_t arg3) 33 { 34 stm32mp1_save_boot_ctx_address(arg0); 35 } 36 37 void bl2_platform_setup(void) 38 { 39 int ret; 40 41 if (dt_check_pmic()) { 42 initialize_pmic(); 43 } 44 45 ret = stm32mp1_ddr_probe(); 46 if (ret < 0) { 47 ERROR("Invalid DDR init: error %d\n", ret); 48 panic(); 49 } 50 51 INFO("BL2 runs SP_MIN setup\n"); 52 } 53 54 void bl2_el3_plat_arch_setup(void) 55 { 56 int32_t result; 57 struct dt_node_info dt_dev_info; 58 const char *board_model; 59 boot_api_context_t *boot_context = 60 (boot_api_context_t *)stm32mp1_get_boot_ctx_address(); 61 uint32_t clk_rate; 62 63 /* 64 * Disable the backup domain write protection. 65 * The protection is enable at each reset by hardware 66 * and must be disabled by software. 67 */ 68 mmio_setbits_32(PWR_BASE + PWR_CR1, PWR_CR1_DBP); 69 70 while ((mmio_read_32(PWR_BASE + PWR_CR1) & PWR_CR1_DBP) == 0U) { 71 ; 72 } 73 74 /* Reset backup domain on cold boot cases */ 75 if ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 76 mmio_setbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); 77 78 while ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_VSWRST) == 79 0U) { 80 ; 81 } 82 83 mmio_clrbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); 84 } 85 86 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 87 BL_CODE_END - BL_CODE_BASE, 88 MT_CODE | MT_SECURE); 89 90 /* Prevent corruption of preloaded BL32 */ 91 mmap_add_region(BL32_BASE, BL32_BASE, 92 BL32_LIMIT - BL32_BASE, 93 MT_MEMORY | MT_RO | MT_SECURE); 94 95 /* Prevent corruption of preloaded Device Tree */ 96 mmap_add_region(DTB_BASE, DTB_BASE, 97 DTB_LIMIT - DTB_BASE, 98 MT_MEMORY | MT_RO | MT_SECURE); 99 100 configure_mmu(); 101 102 generic_delay_timer_init(); 103 104 if (dt_open_and_check() < 0) { 105 panic(); 106 } 107 108 if (stm32mp1_clk_probe() < 0) { 109 panic(); 110 } 111 112 if (stm32mp1_clk_init() < 0) { 113 panic(); 114 } 115 116 result = dt_get_stdout_uart_info(&dt_dev_info); 117 118 if ((result <= 0) || 119 (dt_dev_info.status == 0U) || 120 (dt_dev_info.clock < 0) || 121 (dt_dev_info.reset < 0)) { 122 goto skip_console_init; 123 } 124 125 if (dt_set_stdout_pinctrl() != 0) { 126 goto skip_console_init; 127 } 128 129 if (stm32mp1_clk_enable((unsigned long)dt_dev_info.clock) != 0) { 130 goto skip_console_init; 131 } 132 133 stm32mp1_reset_assert((uint32_t)dt_dev_info.reset); 134 udelay(2); 135 stm32mp1_reset_deassert((uint32_t)dt_dev_info.reset); 136 mdelay(1); 137 138 clk_rate = stm32mp1_clk_get_rate((unsigned long)dt_dev_info.clock); 139 140 if (console_init(dt_dev_info.base, clk_rate, 141 STM32MP1_UART_BAUDRATE) == 0) { 142 panic(); 143 } 144 145 board_model = dt_get_board_model(); 146 if (board_model != NULL) { 147 NOTICE("%s\n", board_model); 148 } 149 150 skip_console_init: 151 152 if (stm32_save_boot_interface(boot_context->boot_interface_selected, 153 boot_context->boot_interface_instance) != 154 0) { 155 ERROR("Cannot save boot interface\n"); 156 } 157 158 stm32mp1_arch_security_setup(); 159 160 stm32mp1_io_setup(); 161 } 162