1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/desc_image_load.h> 16 #include <drivers/delay_timer.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/st/stm32_console.h> 19 #include <drivers/st/stm32mp_pmic.h> 20 #include <drivers/st/stm32mp_reset.h> 21 #include <drivers/st/stm32mp1_clk.h> 22 #include <drivers/st/stm32mp1_pwr.h> 23 #include <drivers/st/stm32mp1_ram.h> 24 #include <drivers/st/stm32mp1_rcc.h> 25 #include <lib/mmio.h> 26 #include <lib/xlat_tables/xlat_tables_v2.h> 27 #include <plat/common/platform.h> 28 29 #include <stm32mp1_context.h> 30 31 static struct console_stm32 console; 32 33 static void print_reset_reason(void) 34 { 35 uint32_t rstsr = mmio_read_32(RCC_BASE + RCC_MP_RSTSCLRR); 36 37 if (rstsr == 0U) { 38 WARN("Reset reason unknown\n"); 39 return; 40 } 41 42 INFO("Reset reason (0x%x):\n", rstsr); 43 44 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) { 45 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) { 46 INFO("System exits from STANDBY\n"); 47 return; 48 } 49 50 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) { 51 INFO("MPU exits from CSTANDBY\n"); 52 return; 53 } 54 } 55 56 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) { 57 INFO(" Power-on Reset (rst_por)\n"); 58 return; 59 } 60 61 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) { 62 INFO(" Brownout Reset (rst_bor)\n"); 63 return; 64 } 65 66 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) { 67 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 68 INFO(" System reset generated by MCU (MCSYSRST)\n"); 69 } else { 70 INFO(" Local reset generated by MCU (MCSYSRST)\n"); 71 } 72 return; 73 } 74 75 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) { 76 INFO(" System reset generated by MPU (MPSYSRST)\n"); 77 return; 78 } 79 80 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) { 81 INFO(" Reset due to a clock failure on HSE\n"); 82 return; 83 } 84 85 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) { 86 INFO(" IWDG1 Reset (rst_iwdg1)\n"); 87 return; 88 } 89 90 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) { 91 INFO(" IWDG2 Reset (rst_iwdg2)\n"); 92 return; 93 } 94 95 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) { 96 INFO(" MPU Processor 0 Reset\n"); 97 return; 98 } 99 100 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) { 101 INFO(" MPU Processor 1 Reset\n"); 102 return; 103 } 104 105 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 106 INFO(" Pad Reset from NRST\n"); 107 return; 108 } 109 110 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) { 111 INFO(" Reset due to a failure of VDD_CORE\n"); 112 return; 113 } 114 115 ERROR(" Unidentified reset reason\n"); 116 } 117 118 void bl2_el3_early_platform_setup(u_register_t arg0, 119 u_register_t arg1 __unused, 120 u_register_t arg2 __unused, 121 u_register_t arg3 __unused) 122 { 123 stm32mp_save_boot_ctx_address(arg0); 124 } 125 126 void bl2_platform_setup(void) 127 { 128 int ret; 129 130 if (dt_check_pmic()) { 131 initialize_pmic(); 132 } 133 134 ret = stm32mp1_ddr_probe(); 135 if (ret < 0) { 136 ERROR("Invalid DDR init: error %d\n", ret); 137 panic(); 138 } 139 140 INFO("BL2 runs SP_MIN setup\n"); 141 } 142 143 void bl2_el3_plat_arch_setup(void) 144 { 145 int32_t result; 146 struct dt_node_info dt_uart_info; 147 const char *board_model; 148 boot_api_context_t *boot_context = 149 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 150 uint32_t clk_rate; 151 152 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 153 BL_CODE_END - BL_CODE_BASE, 154 MT_CODE | MT_SECURE); 155 156 /* Prevent corruption of preloaded BL32 */ 157 mmap_add_region(BL32_BASE, BL32_BASE, 158 BL32_LIMIT - BL32_BASE, 159 MT_MEMORY | MT_RO | MT_SECURE); 160 161 /* Map non secure DDR for BL33 load and DDR training area restore */ 162 mmap_add_region(STM32MP_DDR_BASE, 163 STM32MP_DDR_BASE, 164 STM32MP_DDR_MAX_SIZE, 165 MT_MEMORY | MT_RW | MT_NS); 166 167 /* Prevent corruption of preloaded Device Tree */ 168 mmap_add_region(DTB_BASE, DTB_BASE, 169 DTB_LIMIT - DTB_BASE, 170 MT_MEMORY | MT_RO | MT_SECURE); 171 172 configure_mmu(); 173 174 if (dt_open_and_check() < 0) { 175 panic(); 176 } 177 178 /* 179 * Disable the backup domain write protection. 180 * The protection is enable at each reset by hardware 181 * and must be disabled by software. 182 */ 183 mmio_setbits_32(PWR_BASE + PWR_CR1, PWR_CR1_DBP); 184 185 while ((mmio_read_32(PWR_BASE + PWR_CR1) & PWR_CR1_DBP) == 0U) { 186 ; 187 } 188 189 /* Reset backup domain on cold boot cases */ 190 if ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 191 mmio_setbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); 192 193 while ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_VSWRST) == 194 0U) { 195 ; 196 } 197 198 mmio_clrbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); 199 } 200 201 generic_delay_timer_init(); 202 203 if (stm32mp1_clk_probe() < 0) { 204 panic(); 205 } 206 207 if (stm32mp1_clk_init() < 0) { 208 panic(); 209 } 210 211 result = dt_get_stdout_uart_info(&dt_uart_info); 212 213 if ((result <= 0) || 214 (dt_uart_info.status == 0U) || 215 (dt_uart_info.clock < 0) || 216 (dt_uart_info.reset < 0)) { 217 goto skip_console_init; 218 } 219 220 if (dt_set_stdout_pinctrl() != 0) { 221 goto skip_console_init; 222 } 223 224 if (stm32mp_clk_enable((unsigned long)dt_uart_info.clock) != 0) { 225 goto skip_console_init; 226 } 227 228 stm32mp_reset_assert((uint32_t)dt_uart_info.reset); 229 udelay(2); 230 stm32mp_reset_deassert((uint32_t)dt_uart_info.reset); 231 mdelay(1); 232 233 clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock); 234 235 if (console_stm32_register(dt_uart_info.base, clk_rate, 236 STM32MP_UART_BAUDRATE, &console) == 0) { 237 panic(); 238 } 239 240 board_model = dt_get_board_model(); 241 if (board_model != NULL) { 242 NOTICE("Model: %s\n", board_model); 243 } 244 245 skip_console_init: 246 247 if (stm32_save_boot_interface(boot_context->boot_interface_selected, 248 boot_context->boot_interface_instance) != 249 0) { 250 ERROR("Cannot save boot interface\n"); 251 } 252 253 stm32mp1_arch_security_setup(); 254 255 print_reset_reason(); 256 257 stm32mp_io_setup(); 258 } 259