1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/desc_image_load.h> 15 #include <drivers/generic_delay_timer.h> 16 #include <drivers/mmc.h> 17 #include <drivers/st/bsec.h> 18 #include <drivers/st/stm32_iwdg.h> 19 #include <drivers/st/stm32_uart.h> 20 #include <drivers/st/stm32mp1_clk.h> 21 #include <drivers/st/stm32mp1_pwr.h> 22 #include <drivers/st/stm32mp1_ram.h> 23 #include <drivers/st/stm32mp_pmic.h> 24 #include <lib/fconf/fconf.h> 25 #include <lib/fconf/fconf_dyn_cfg_getter.h> 26 #include <lib/mmio.h> 27 #include <lib/optee_utils.h> 28 #include <lib/xlat_tables/xlat_tables_v2.h> 29 #include <plat/common/platform.h> 30 31 #include <platform_def.h> 32 #include <stm32mp1_dbgmcu.h> 33 34 static struct stm32mp_auth_ops stm32mp1_auth_ops; 35 36 static void print_reset_reason(void) 37 { 38 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR); 39 40 if (rstsr == 0U) { 41 WARN("Reset reason unknown\n"); 42 return; 43 } 44 45 INFO("Reset reason (0x%x):\n", rstsr); 46 47 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) { 48 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) { 49 INFO("System exits from STANDBY\n"); 50 return; 51 } 52 53 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) { 54 INFO("MPU exits from CSTANDBY\n"); 55 return; 56 } 57 } 58 59 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) { 60 INFO(" Power-on Reset (rst_por)\n"); 61 return; 62 } 63 64 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) { 65 INFO(" Brownout Reset (rst_bor)\n"); 66 return; 67 } 68 69 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) { 70 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 71 INFO(" System reset generated by MCU (MCSYSRST)\n"); 72 } else { 73 INFO(" Local reset generated by MCU (MCSYSRST)\n"); 74 } 75 return; 76 } 77 78 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) { 79 INFO(" System reset generated by MPU (MPSYSRST)\n"); 80 return; 81 } 82 83 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) { 84 INFO(" Reset due to a clock failure on HSE\n"); 85 return; 86 } 87 88 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) { 89 INFO(" IWDG1 Reset (rst_iwdg1)\n"); 90 return; 91 } 92 93 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) { 94 INFO(" IWDG2 Reset (rst_iwdg2)\n"); 95 return; 96 } 97 98 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) { 99 INFO(" MPU Processor 0 Reset\n"); 100 return; 101 } 102 103 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) { 104 INFO(" MPU Processor 1 Reset\n"); 105 return; 106 } 107 108 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 109 INFO(" Pad Reset from NRST\n"); 110 return; 111 } 112 113 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) { 114 INFO(" Reset due to a failure of VDD_CORE\n"); 115 return; 116 } 117 118 ERROR(" Unidentified reset reason\n"); 119 } 120 121 void bl2_el3_early_platform_setup(u_register_t arg0, 122 u_register_t arg1 __unused, 123 u_register_t arg2 __unused, 124 u_register_t arg3 __unused) 125 { 126 stm32mp_save_boot_ctx_address(arg0); 127 } 128 129 void bl2_platform_setup(void) 130 { 131 int ret; 132 133 if (dt_pmic_status() > 0) { 134 initialize_pmic(); 135 } 136 137 ret = stm32mp1_ddr_probe(); 138 if (ret < 0) { 139 ERROR("Invalid DDR init: error %d\n", ret); 140 panic(); 141 } 142 143 /* Map DDR for binary load, now with cacheable attribute */ 144 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, 145 STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE); 146 if (ret < 0) { 147 ERROR("DDR mapping: error %d\n", ret); 148 panic(); 149 } 150 151 #if STM32MP_USE_STM32IMAGE 152 #ifdef AARCH32_SP_OPTEE 153 INFO("BL2 runs OP-TEE setup\n"); 154 #else 155 INFO("BL2 runs SP_MIN setup\n"); 156 #endif 157 #endif /* STM32MP_USE_STM32IMAGE */ 158 } 159 160 void bl2_el3_plat_arch_setup(void) 161 { 162 const char *board_model; 163 boot_api_context_t *boot_context = 164 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 165 uintptr_t pwr_base; 166 uintptr_t rcc_base; 167 168 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 169 BL_CODE_END - BL_CODE_BASE, 170 MT_CODE | MT_SECURE); 171 172 #if STM32MP_USE_STM32IMAGE 173 #ifdef AARCH32_SP_OPTEE 174 mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE, 175 STM32MP_OPTEE_SIZE, 176 MT_MEMORY | MT_RW | MT_SECURE); 177 #else 178 /* Prevent corruption of preloaded BL32 */ 179 mmap_add_region(BL32_BASE, BL32_BASE, 180 BL32_LIMIT - BL32_BASE, 181 MT_RO_DATA | MT_SECURE); 182 #endif 183 #endif /* STM32MP_USE_STM32IMAGE */ 184 185 /* Prevent corruption of preloaded Device Tree */ 186 mmap_add_region(DTB_BASE, DTB_BASE, 187 DTB_LIMIT - DTB_BASE, 188 MT_RO_DATA | MT_SECURE); 189 190 configure_mmu(); 191 192 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) { 193 panic(); 194 } 195 196 pwr_base = stm32mp_pwr_base(); 197 rcc_base = stm32mp_rcc_base(); 198 199 /* 200 * Disable the backup domain write protection. 201 * The protection is enable at each reset by hardware 202 * and must be disabled by software. 203 */ 204 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP); 205 206 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) { 207 ; 208 } 209 210 if (bsec_probe() != 0) { 211 panic(); 212 } 213 214 /* Reset backup domain on cold boot cases */ 215 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 216 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 217 218 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 219 0U) { 220 ; 221 } 222 223 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 224 } 225 226 /* Disable MCKPROT */ 227 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); 228 229 /* 230 * Set minimum reset pulse duration to 31ms for discrete power 231 * supplied boards. 232 */ 233 if (dt_pmic_status() <= 0) { 234 mmio_clrsetbits_32(rcc_base + RCC_RDLSICR, 235 RCC_RDLSICR_MRD_MASK, 236 31U << RCC_RDLSICR_MRD_SHIFT); 237 } 238 239 generic_delay_timer_init(); 240 241 #if STM32MP_UART_PROGRAMMER 242 /* Disable programmer UART before changing clock tree */ 243 if (boot_context->boot_interface_selected == 244 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) { 245 uintptr_t uart_prog_addr = 246 get_uart_address(boot_context->boot_interface_instance); 247 248 stm32_uart_stop(uart_prog_addr); 249 } 250 #endif 251 if (stm32mp1_clk_probe() < 0) { 252 panic(); 253 } 254 255 if (stm32mp1_clk_init() < 0) { 256 panic(); 257 } 258 259 stm32mp1_syscfg_init(); 260 261 stm32_save_boot_interface(boot_context->boot_interface_selected, 262 boot_context->boot_interface_instance); 263 264 #if STM32MP_USB_PROGRAMMER 265 /* Deconfigure all UART RX pins configured by ROM code */ 266 stm32mp1_deconfigure_uart_pins(); 267 #endif 268 269 if (stm32mp_uart_console_setup() != 0) { 270 goto skip_console_init; 271 } 272 273 stm32mp_print_cpuinfo(); 274 275 board_model = dt_get_board_model(); 276 if (board_model != NULL) { 277 NOTICE("Model: %s\n", board_model); 278 } 279 280 stm32mp_print_boardinfo(); 281 282 if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) { 283 NOTICE("Bootrom authentication %s\n", 284 (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ? 285 "failed" : "succeeded"); 286 } 287 288 skip_console_init: 289 if (stm32_iwdg_init() < 0) { 290 panic(); 291 } 292 293 stm32_iwdg_refresh(); 294 295 stm32mp1_auth_ops.check_key = boot_context->bootrom_ecdsa_check_key; 296 stm32mp1_auth_ops.verify_signature = 297 boot_context->bootrom_ecdsa_verify_signature; 298 299 stm32mp_init_auth(&stm32mp1_auth_ops); 300 301 stm32mp1_arch_security_setup(); 302 303 print_reset_reason(); 304 305 #if !STM32MP_USE_STM32IMAGE 306 fconf_populate("TB_FW", STM32MP_DTB_BASE); 307 #endif /* !STM32MP_USE_STM32IMAGE */ 308 309 stm32mp_io_setup(); 310 } 311 312 /******************************************************************************* 313 * This function can be used by the platforms to update/use image 314 * information for given `image_id`. 315 ******************************************************************************/ 316 int bl2_plat_handle_post_image_load(unsigned int image_id) 317 { 318 int err = 0; 319 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 320 bl_mem_params_node_t *bl32_mem_params; 321 bl_mem_params_node_t *pager_mem_params __unused; 322 bl_mem_params_node_t *paged_mem_params __unused; 323 #if !STM32MP_USE_STM32IMAGE 324 const struct dyn_cfg_dtb_info_t *config_info; 325 bl_mem_params_node_t *tos_fw_mem_params; 326 unsigned int i; 327 unsigned int idx; 328 unsigned long long ddr_top __unused; 329 const unsigned int image_ids[] = { 330 BL32_IMAGE_ID, 331 BL33_IMAGE_ID, 332 HW_CONFIG_ID, 333 TOS_FW_CONFIG_ID, 334 }; 335 #endif /* !STM32MP_USE_STM32IMAGE */ 336 337 assert(bl_mem_params != NULL); 338 339 switch (image_id) { 340 #if !STM32MP_USE_STM32IMAGE 341 case FW_CONFIG_ID: 342 /* Set global DTB info for fixed fw_config information */ 343 set_config_info(STM32MP_FW_CONFIG_BASE, STM32MP_FW_CONFIG_MAX_SIZE, FW_CONFIG_ID); 344 fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE); 345 346 idx = dyn_cfg_dtb_info_get_index(TOS_FW_CONFIG_ID); 347 348 /* Iterate through all the fw config IDs */ 349 for (i = 0U; i < ARRAY_SIZE(image_ids); i++) { 350 if ((image_ids[i] == TOS_FW_CONFIG_ID) && (idx == FCONF_INVALID_IDX)) { 351 continue; 352 } 353 354 bl_mem_params = get_bl_mem_params_node(image_ids[i]); 355 assert(bl_mem_params != NULL); 356 357 config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]); 358 if (config_info == NULL) { 359 continue; 360 } 361 362 bl_mem_params->image_info.image_base = config_info->config_addr; 363 bl_mem_params->image_info.image_max_size = config_info->config_max_size; 364 365 bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING; 366 367 switch (image_ids[i]) { 368 case BL32_IMAGE_ID: 369 bl_mem_params->ep_info.pc = config_info->config_addr; 370 371 /* In case of OPTEE, initialize address space with tos_fw addr */ 372 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 373 pager_mem_params->image_info.image_base = config_info->config_addr; 374 pager_mem_params->image_info.image_max_size = 375 config_info->config_max_size; 376 377 /* Init base and size for pager if exist */ 378 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 379 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 380 (dt_get_ddr_size() - STM32MP_DDR_S_SIZE - 381 STM32MP_DDR_SHMEM_SIZE); 382 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; 383 break; 384 385 case BL33_IMAGE_ID: 386 bl_mem_params->ep_info.pc = config_info->config_addr; 387 break; 388 389 case HW_CONFIG_ID: 390 case TOS_FW_CONFIG_ID: 391 break; 392 393 default: 394 return -EINVAL; 395 } 396 } 397 break; 398 #endif /* !STM32MP_USE_STM32IMAGE */ 399 400 case BL32_IMAGE_ID: 401 if (optee_header_is_valid(bl_mem_params->image_info.image_base)) { 402 /* BL32 is OP-TEE header */ 403 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 404 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 405 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 406 assert((pager_mem_params != NULL) && (paged_mem_params != NULL)); 407 408 #if STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) 409 /* Set OP-TEE extra image load areas at run-time */ 410 pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE; 411 pager_mem_params->image_info.image_max_size = STM32MP_OPTEE_SIZE; 412 413 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 414 dt_get_ddr_size() - 415 STM32MP_DDR_S_SIZE - 416 STM32MP_DDR_SHMEM_SIZE; 417 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; 418 #endif /* STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) */ 419 420 err = parse_optee_header(&bl_mem_params->ep_info, 421 &pager_mem_params->image_info, 422 &paged_mem_params->image_info); 423 if (err) { 424 ERROR("OPTEE header parse error.\n"); 425 panic(); 426 } 427 428 /* Set optee boot info from parsed header data */ 429 bl_mem_params->ep_info.args.arg0 = paged_mem_params->image_info.image_base; 430 bl_mem_params->ep_info.args.arg1 = 0; /* Unused */ 431 bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */ 432 } else { 433 #if !STM32MP_USE_STM32IMAGE 434 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 435 tos_fw_mem_params = get_bl_mem_params_node(TOS_FW_CONFIG_ID); 436 bl_mem_params->image_info.image_max_size += 437 tos_fw_mem_params->image_info.image_max_size; 438 #endif /* !STM32MP_USE_STM32IMAGE */ 439 bl_mem_params->ep_info.args.arg0 = 0; 440 } 441 break; 442 443 case BL33_IMAGE_ID: 444 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); 445 assert(bl32_mem_params != NULL); 446 bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; 447 break; 448 449 default: 450 /* Do nothing in default case */ 451 break; 452 } 453 454 #if STM32MP_SDMMC || STM32MP_EMMC 455 /* 456 * Invalidate remaining data read from MMC but not flushed by load_image_flush(). 457 * We take the worst case which is 2 MMC blocks. 458 */ 459 if ((image_id != FW_CONFIG_ID) && 460 ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) { 461 inv_dcache_range(bl_mem_params->image_info.image_base + 462 bl_mem_params->image_info.image_size, 463 2U * MMC_BLOCK_SIZE); 464 } 465 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 466 467 return err; 468 } 469 470 void bl2_el3_plat_prepare_exit(void) 471 { 472 uint16_t boot_itf = stm32mp_get_boot_itf_selected(); 473 474 switch (boot_itf) { 475 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 476 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART: 477 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 478 /* Invalidate the downloaded buffer used with io_memmap */ 479 inv_dcache_range(DWL_BUFFER_BASE, DWL_BUFFER_SIZE); 480 break; 481 #endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */ 482 default: 483 /* Do nothing in default case */ 484 break; 485 } 486 487 stm32mp1_security_setup(); 488 } 489