1*4353bb20SYann Gautier /* 2*4353bb20SYann Gautier * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*4353bb20SYann Gautier * 4*4353bb20SYann Gautier * SPDX-License-Identifier: BSD-3-Clause 5*4353bb20SYann Gautier */ 6*4353bb20SYann Gautier 7*4353bb20SYann Gautier #include <arch_helpers.h> 8*4353bb20SYann Gautier #include <assert.h> 9*4353bb20SYann Gautier #include <bl_common.h> 10*4353bb20SYann Gautier #include <boot_api.h> 11*4353bb20SYann Gautier #include <console.h> 12*4353bb20SYann Gautier #include <debug.h> 13*4353bb20SYann Gautier #include <delay_timer.h> 14*4353bb20SYann Gautier #include <desc_image_load.h> 15*4353bb20SYann Gautier #include <generic_delay_timer.h> 16*4353bb20SYann Gautier #include <mmio.h> 17*4353bb20SYann Gautier #include <platform.h> 18*4353bb20SYann Gautier #include <platform_def.h> 19*4353bb20SYann Gautier #include <stm32mp1_private.h> 20*4353bb20SYann Gautier #include <stm32mp1_pwr.h> 21*4353bb20SYann Gautier #include <stm32mp1_rcc.h> 22*4353bb20SYann Gautier #include <string.h> 23*4353bb20SYann Gautier #include <xlat_tables_v2.h> 24*4353bb20SYann Gautier 25*4353bb20SYann Gautier void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1, 26*4353bb20SYann Gautier u_register_t arg2, u_register_t arg3) 27*4353bb20SYann Gautier { 28*4353bb20SYann Gautier stm32mp1_save_boot_ctx_address(arg0); 29*4353bb20SYann Gautier } 30*4353bb20SYann Gautier 31*4353bb20SYann Gautier void bl2_platform_setup(void) 32*4353bb20SYann Gautier { 33*4353bb20SYann Gautier INFO("BL2 runs SP_MIN setup\n"); 34*4353bb20SYann Gautier } 35*4353bb20SYann Gautier 36*4353bb20SYann Gautier void bl2_el3_plat_arch_setup(void) 37*4353bb20SYann Gautier { 38*4353bb20SYann Gautier /* 39*4353bb20SYann Gautier * Disable the backup domain write protection. 40*4353bb20SYann Gautier * The protection is enable at each reset by hardware 41*4353bb20SYann Gautier * and must be disabled by software. 42*4353bb20SYann Gautier */ 43*4353bb20SYann Gautier mmio_setbits_32(PWR_BASE + PWR_CR1, PWR_CR1_DBP); 44*4353bb20SYann Gautier 45*4353bb20SYann Gautier while ((mmio_read_32(PWR_BASE + PWR_CR1) & PWR_CR1_DBP) == 0U) { 46*4353bb20SYann Gautier ; 47*4353bb20SYann Gautier } 48*4353bb20SYann Gautier 49*4353bb20SYann Gautier /* Reset backup domain on cold boot cases */ 50*4353bb20SYann Gautier if ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 51*4353bb20SYann Gautier mmio_setbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); 52*4353bb20SYann Gautier 53*4353bb20SYann Gautier while ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_VSWRST) == 54*4353bb20SYann Gautier 0U) { 55*4353bb20SYann Gautier ; 56*4353bb20SYann Gautier } 57*4353bb20SYann Gautier 58*4353bb20SYann Gautier mmio_clrbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); 59*4353bb20SYann Gautier } 60*4353bb20SYann Gautier 61*4353bb20SYann Gautier mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 62*4353bb20SYann Gautier BL_CODE_END - BL_CODE_BASE, 63*4353bb20SYann Gautier MT_CODE | MT_SECURE); 64*4353bb20SYann Gautier 65*4353bb20SYann Gautier /* Prevent corruption of preloaded BL32 */ 66*4353bb20SYann Gautier mmap_add_region(BL32_BASE, BL32_BASE, 67*4353bb20SYann Gautier BL32_LIMIT - BL32_BASE, 68*4353bb20SYann Gautier MT_MEMORY | MT_RO | MT_SECURE); 69*4353bb20SYann Gautier 70*4353bb20SYann Gautier /* Prevent corruption of preloaded Device Tree */ 71*4353bb20SYann Gautier mmap_add_region(DTB_BASE, DTB_BASE, 72*4353bb20SYann Gautier DTB_LIMIT - DTB_BASE, 73*4353bb20SYann Gautier MT_MEMORY | MT_RO | MT_SECURE); 74*4353bb20SYann Gautier 75*4353bb20SYann Gautier configure_mmu(); 76*4353bb20SYann Gautier 77*4353bb20SYann Gautier generic_delay_timer_init(); 78*4353bb20SYann Gautier 79*4353bb20SYann Gautier stm32mp1_io_setup(); 80*4353bb20SYann Gautier } 81