1 /* 2 * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/bl_common.h> 8 #include <common/debug.h> 9 #include <drivers/arm/gicv2.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <lib/utils.h> 12 #include <libfdt.h> 13 #include <plat/common/platform.h> 14 15 #include <platform_def.h> 16 17 struct stm32mp_gic_instance { 18 uint32_t cells; 19 uint32_t phandle_node; 20 }; 21 22 /****************************************************************************** 23 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 24 * interrupts. 25 *****************************************************************************/ 26 static const interrupt_prop_t stm32mp_interrupt_props[] = { 27 PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0), 28 PLATFORM_G0_PROPS(GICV2_INTR_GROUP0) 29 }; 30 31 /* Fix target_mask_array as secondary core is not able to initialize it */ 32 static unsigned int target_mask_array[PLATFORM_CORE_COUNT] = {1, 2}; 33 34 static gicv2_driver_data_t platform_gic_data = { 35 .interrupt_props = stm32mp_interrupt_props, 36 .interrupt_props_num = ARRAY_SIZE(stm32mp_interrupt_props), 37 .target_masks = target_mask_array, 38 .target_masks_num = ARRAY_SIZE(target_mask_array), 39 }; 40 41 static struct stm32mp_gic_instance stm32mp_gic; 42 43 void stm32mp_gic_init(void) 44 { 45 int node; 46 void *fdt; 47 const fdt32_t *cuint; 48 struct dt_node_info dt_gic; 49 50 if (fdt_get_address(&fdt) == 0) { 51 panic(); 52 } 53 54 node = dt_get_node(&dt_gic, -1, "arm,cortex-a7-gic"); 55 if (node < 0) { 56 panic(); 57 } 58 59 platform_gic_data.gicd_base = dt_gic.base; 60 61 cuint = fdt_getprop(fdt, node, "reg", NULL); 62 if (cuint == NULL) { 63 panic(); 64 } 65 66 platform_gic_data.gicc_base = fdt32_to_cpu(*(cuint + 2)); 67 68 cuint = fdt_getprop(fdt, node, "#interrupt-cells", NULL); 69 if (cuint == NULL) { 70 panic(); 71 } 72 73 stm32mp_gic.cells = fdt32_to_cpu(*cuint); 74 75 stm32mp_gic.phandle_node = fdt_get_phandle(fdt, node); 76 if (stm32mp_gic.phandle_node == 0U) { 77 panic(); 78 } 79 80 gicv2_driver_init(&platform_gic_data); 81 gicv2_distif_init(); 82 83 stm32mp_gic_pcpu_init(); 84 } 85 86 void stm32mp_gic_pcpu_init(void) 87 { 88 gicv2_pcpu_distif_init(); 89 gicv2_set_pe_target_mask(plat_my_core_pos()); 90 gicv2_cpuif_enable(); 91 } 92