1 /* 2 * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <drivers/clk.h> 13 #include <drivers/delay_timer.h> 14 #include <drivers/st/stm32_console.h> 15 #include <drivers/st/stm32mp_clkfunc.h> 16 #include <drivers/st/stm32mp_reset.h> 17 #include <lib/mmio.h> 18 #include <lib/smccc.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 #include <services/arm_arch_svc.h> 22 23 #include <platform_def.h> 24 25 #define HEADER_VERSION_MAJOR_MASK GENMASK(23, 16) 26 #define RESET_TIMEOUT_US_1MS 1000U 27 28 /* Internal layout of the 32bit OTP word board_id */ 29 #define BOARD_ID_BOARD_NB_MASK GENMASK_32(31, 16) 30 #define BOARD_ID_BOARD_NB_SHIFT 16 31 #define BOARD_ID_VARCPN_MASK GENMASK_32(15, 12) 32 #define BOARD_ID_VARCPN_SHIFT 12 33 #define BOARD_ID_REVISION_MASK GENMASK_32(11, 8) 34 #define BOARD_ID_REVISION_SHIFT 8 35 #define BOARD_ID_VARFG_MASK GENMASK_32(7, 4) 36 #define BOARD_ID_VARFG_SHIFT 4 37 #define BOARD_ID_BOM_MASK GENMASK_32(3, 0) 38 39 #define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \ 40 BOARD_ID_BOARD_NB_SHIFT) 41 #define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \ 42 BOARD_ID_VARCPN_SHIFT) 43 #define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \ 44 BOARD_ID_REVISION_SHIFT) 45 #define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \ 46 BOARD_ID_VARFG_SHIFT) 47 #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK) 48 49 #define BOOT_AUTH_MASK GENMASK_32(23, 20) 50 #define BOOT_AUTH_SHIFT 20 51 #define BOOT_PART_MASK GENMASK_32(19, 16) 52 #define BOOT_PART_SHIFT 16 53 #define BOOT_ITF_MASK GENMASK_32(15, 12) 54 #define BOOT_ITF_SHIFT 12 55 #define BOOT_INST_MASK GENMASK_32(11, 8) 56 #define BOOT_INST_SHIFT 8 57 58 static console_t console; 59 60 uintptr_t plat_get_ns_image_entrypoint(void) 61 { 62 return BL33_BASE; 63 } 64 65 unsigned int plat_get_syscnt_freq2(void) 66 { 67 return read_cntfrq_el0(); 68 } 69 70 static uintptr_t boot_ctx_address; 71 static uint16_t boot_itf_selected; 72 73 void stm32mp_save_boot_ctx_address(uintptr_t address) 74 { 75 boot_api_context_t *boot_context = (boot_api_context_t *)address; 76 77 boot_ctx_address = address; 78 boot_itf_selected = boot_context->boot_interface_selected; 79 } 80 81 uintptr_t stm32mp_get_boot_ctx_address(void) 82 { 83 return boot_ctx_address; 84 } 85 86 uint16_t stm32mp_get_boot_itf_selected(void) 87 { 88 return boot_itf_selected; 89 } 90 91 uintptr_t stm32mp_ddrctrl_base(void) 92 { 93 return DDRCTRL_BASE; 94 } 95 96 uintptr_t stm32mp_ddrphyc_base(void) 97 { 98 return DDRPHYC_BASE; 99 } 100 101 uintptr_t stm32mp_pwr_base(void) 102 { 103 return PWR_BASE; 104 } 105 106 uintptr_t stm32mp_rcc_base(void) 107 { 108 return RCC_BASE; 109 } 110 111 bool stm32mp_lock_available(void) 112 { 113 const uint32_t c_m_bits = SCTLR_M_BIT | SCTLR_C_BIT; 114 115 /* The spinlocks are used only when MMU and data cache are enabled */ 116 return (read_sctlr() & c_m_bits) == c_m_bits; 117 } 118 119 int stm32mp_map_ddr_non_cacheable(void) 120 { 121 return mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, 122 STM32MP_DDR_MAX_SIZE, 123 MT_NON_CACHEABLE | MT_RW | MT_SECURE); 124 } 125 126 int stm32mp_unmap_ddr(void) 127 { 128 return mmap_remove_dynamic_region(STM32MP_DDR_BASE, 129 STM32MP_DDR_MAX_SIZE); 130 } 131 132 int stm32_get_otp_index(const char *otp_name, uint32_t *otp_idx, 133 uint32_t *otp_len) 134 { 135 assert(otp_name != NULL); 136 assert(otp_idx != NULL); 137 138 return dt_find_otp_name(otp_name, otp_idx, otp_len); 139 } 140 141 int stm32_get_otp_value(const char *otp_name, uint32_t *otp_val) 142 { 143 uint32_t otp_idx; 144 145 assert(otp_name != NULL); 146 assert(otp_val != NULL); 147 148 if (stm32_get_otp_index(otp_name, &otp_idx, NULL) != 0) { 149 return -1; 150 } 151 152 if (stm32_get_otp_value_from_idx(otp_idx, otp_val) != 0) { 153 ERROR("BSEC: %s Read Error\n", otp_name); 154 return -1; 155 } 156 157 return 0; 158 } 159 160 int stm32_get_otp_value_from_idx(const uint32_t otp_idx, uint32_t *otp_val) 161 { 162 uint32_t ret = BSEC_NOT_SUPPORTED; 163 164 assert(otp_val != NULL); 165 166 #if defined(IMAGE_BL2) 167 ret = bsec_shadow_read_otp(otp_val, otp_idx); 168 #elif defined(IMAGE_BL32) 169 ret = bsec_read_otp(otp_val, otp_idx); 170 #else 171 #error "Not supported" 172 #endif 173 if (ret != BSEC_OK) { 174 ERROR("BSEC: idx=%u Read Error\n", otp_idx); 175 return -1; 176 } 177 178 return 0; 179 } 180 181 #if defined(IMAGE_BL2) 182 static void reset_uart(uint32_t reset) 183 { 184 int ret; 185 186 ret = stm32mp_reset_assert(reset, RESET_TIMEOUT_US_1MS); 187 if (ret != 0) { 188 panic(); 189 } 190 191 udelay(2); 192 193 ret = stm32mp_reset_deassert(reset, RESET_TIMEOUT_US_1MS); 194 if (ret != 0) { 195 panic(); 196 } 197 198 mdelay(1); 199 } 200 #endif 201 202 static void set_console(uintptr_t base, uint32_t clk_rate) 203 { 204 unsigned int console_flags; 205 206 if (console_stm32_register(base, clk_rate, 207 (uint32_t)STM32MP_UART_BAUDRATE, &console) == 0) { 208 panic(); 209 } 210 211 console_flags = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH | 212 CONSOLE_FLAG_TRANSLATE_CRLF; 213 #if !defined(IMAGE_BL2) && defined(DEBUG) 214 console_flags |= CONSOLE_FLAG_RUNTIME; 215 #endif 216 217 console_set_scope(&console, console_flags); 218 } 219 220 int stm32mp_uart_console_setup(void) 221 { 222 struct dt_node_info dt_uart_info; 223 uint32_t clk_rate = 0U; 224 int result; 225 uint32_t boot_itf __unused; 226 uint32_t boot_instance __unused; 227 228 result = dt_get_stdout_uart_info(&dt_uart_info); 229 230 if ((result <= 0) || 231 (dt_uart_info.status == DT_DISABLED)) { 232 return -ENODEV; 233 } 234 235 #if defined(IMAGE_BL2) 236 if ((dt_uart_info.clock < 0) || 237 (dt_uart_info.reset < 0)) { 238 return -ENODEV; 239 } 240 #endif 241 242 #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2) 243 stm32_get_boot_interface(&boot_itf, &boot_instance); 244 245 if ((boot_itf == BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) && 246 (get_uart_address(boot_instance) == dt_uart_info.base)) { 247 return -EACCES; 248 } 249 #endif 250 251 #if defined(IMAGE_BL2) 252 if (dt_set_stdout_pinctrl() != 0) { 253 return -ENODEV; 254 } 255 256 clk_enable((unsigned long)dt_uart_info.clock); 257 258 reset_uart((uint32_t)dt_uart_info.reset); 259 260 clk_rate = clk_get_rate((unsigned long)dt_uart_info.clock); 261 #endif 262 263 set_console(dt_uart_info.base, clk_rate); 264 265 return 0; 266 } 267 268 #if STM32MP_EARLY_CONSOLE 269 void stm32mp_setup_early_console(void) 270 { 271 #if defined(IMAGE_BL2) || STM32MP_RECONFIGURE_CONSOLE 272 plat_crash_console_init(); 273 #endif 274 set_console(STM32MP_DEBUG_USART_BASE, STM32MP_DEBUG_USART_CLK_FRQ); 275 NOTICE("Early console setup\n"); 276 } 277 #endif /* STM32MP_EARLY_CONSOLE */ 278 279 /***************************************************************************** 280 * plat_is_smccc_feature_available() - This function checks whether SMCCC 281 * feature is availabile for platform. 282 * @fid: SMCCC function id 283 * 284 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and 285 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise. 286 *****************************************************************************/ 287 int32_t plat_is_smccc_feature_available(u_register_t fid) 288 { 289 switch (fid) { 290 case SMCCC_ARCH_SOC_ID: 291 return SMC_ARCH_CALL_SUCCESS; 292 default: 293 return SMC_ARCH_CALL_NOT_SUPPORTED; 294 } 295 } 296 297 /* Get SOC version */ 298 int32_t plat_get_soc_version(void) 299 { 300 uint32_t chip_id = stm32mp_get_chip_dev_id(); 301 uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_ST_BKID, JEDEC_ST_MFID); 302 303 return (int32_t)(manfid | (chip_id & SOC_ID_IMPL_DEF_MASK)); 304 } 305 306 /* Get SOC revision */ 307 int32_t plat_get_soc_revision(void) 308 { 309 return (int32_t)(stm32mp_get_chip_version() & SOC_ID_REV_MASK); 310 } 311 312 void stm32_display_board_info(uint32_t board_id) 313 { 314 char rev[2]; 315 316 rev[0] = BOARD_ID2REV(board_id) - 1 + 'A'; 317 rev[1] = '\0'; 318 NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n", 319 BOARD_ID2NB(board_id), 320 BOARD_ID2VARCPN(board_id), 321 BOARD_ID2VARFG(board_id), 322 rev, 323 BOARD_ID2BOM(board_id)); 324 } 325 326 void stm32_save_boot_info(boot_api_context_t *boot_context) 327 { 328 uint32_t auth_status; 329 330 assert(boot_context->boot_interface_instance <= (BOOT_INST_MASK >> BOOT_INST_SHIFT)); 331 assert(boot_context->boot_interface_selected <= (BOOT_ITF_MASK >> BOOT_ITF_SHIFT)); 332 assert(boot_context->boot_partition_used_toboot <= (BOOT_PART_MASK >> BOOT_PART_SHIFT)); 333 334 switch (boot_context->auth_status) { 335 case BOOT_API_CTX_AUTH_NO: 336 auth_status = 0x0U; 337 break; 338 339 case BOOT_API_CTX_AUTH_SUCCESS: 340 auth_status = 0x2U; 341 break; 342 343 case BOOT_API_CTX_AUTH_FAILED: 344 default: 345 auth_status = 0x1U; 346 break; 347 } 348 349 clk_enable(TAMP_BKP_REG_CLK); 350 351 mmio_clrsetbits_32(stm32_get_bkpr_boot_mode_addr(), 352 BOOT_ITF_MASK | BOOT_INST_MASK | BOOT_PART_MASK | BOOT_AUTH_MASK, 353 (boot_context->boot_interface_instance << BOOT_INST_SHIFT) | 354 (boot_context->boot_interface_selected << BOOT_ITF_SHIFT) | 355 (boot_context->boot_partition_used_toboot << BOOT_PART_SHIFT) | 356 (auth_status << BOOT_AUTH_SHIFT)); 357 358 clk_disable(TAMP_BKP_REG_CLK); 359 } 360 361 void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance) 362 { 363 static uint32_t itf; 364 365 if (itf == 0U) { 366 clk_enable(TAMP_BKP_REG_CLK); 367 368 itf = mmio_read_32(stm32_get_bkpr_boot_mode_addr()) & 369 (BOOT_ITF_MASK | BOOT_INST_MASK); 370 371 clk_disable(TAMP_BKP_REG_CLK); 372 } 373 374 *interface = (itf & BOOT_ITF_MASK) >> BOOT_ITF_SHIFT; 375 *instance = (itf & BOOT_INST_MASK) >> BOOT_INST_SHIFT; 376 } 377