1 /* 2 * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <drivers/clk.h> 13 #include <drivers/delay_timer.h> 14 #include <drivers/st/stm32_console.h> 15 #include <drivers/st/stm32mp_clkfunc.h> 16 #include <drivers/st/stm32mp_reset.h> 17 #include <lib/mmio.h> 18 #include <lib/smccc.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 #include <services/arm_arch_svc.h> 22 23 #include <platform_def.h> 24 25 #define HEADER_VERSION_MAJOR_MASK GENMASK(23, 16) 26 #define RESET_TIMEOUT_US_1MS 1000U 27 28 #define BOOT_AUTH_MASK GENMASK_32(23, 20) 29 #define BOOT_AUTH_SHIFT 20 30 #define BOOT_PART_MASK GENMASK_32(19, 16) 31 #define BOOT_PART_SHIFT 16 32 #define BOOT_ITF_MASK GENMASK_32(15, 12) 33 #define BOOT_ITF_SHIFT 12 34 #define BOOT_INST_MASK GENMASK_32(11, 8) 35 #define BOOT_INST_SHIFT 8 36 37 static console_t console; 38 39 uintptr_t plat_get_ns_image_entrypoint(void) 40 { 41 return BL33_BASE; 42 } 43 44 unsigned int plat_get_syscnt_freq2(void) 45 { 46 return read_cntfrq_el0(); 47 } 48 49 static uintptr_t boot_ctx_address; 50 static uint16_t boot_itf_selected; 51 52 void stm32mp_save_boot_ctx_address(uintptr_t address) 53 { 54 boot_api_context_t *boot_context = (boot_api_context_t *)address; 55 56 boot_ctx_address = address; 57 boot_itf_selected = boot_context->boot_interface_selected; 58 } 59 60 uintptr_t stm32mp_get_boot_ctx_address(void) 61 { 62 return boot_ctx_address; 63 } 64 65 uint16_t stm32mp_get_boot_itf_selected(void) 66 { 67 return boot_itf_selected; 68 } 69 70 uintptr_t stm32mp_ddrctrl_base(void) 71 { 72 return DDRCTRL_BASE; 73 } 74 75 uintptr_t stm32mp_ddrphyc_base(void) 76 { 77 return DDRPHYC_BASE; 78 } 79 80 uintptr_t stm32mp_pwr_base(void) 81 { 82 return PWR_BASE; 83 } 84 85 uintptr_t stm32mp_rcc_base(void) 86 { 87 return RCC_BASE; 88 } 89 90 bool stm32mp_lock_available(void) 91 { 92 const uint32_t c_m_bits = SCTLR_M_BIT | SCTLR_C_BIT; 93 94 /* The spinlocks are used only when MMU and data cache are enabled */ 95 return (read_sctlr() & c_m_bits) == c_m_bits; 96 } 97 98 int stm32mp_map_ddr_non_cacheable(void) 99 { 100 return mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, 101 STM32MP_DDR_MAX_SIZE, 102 MT_NON_CACHEABLE | MT_RW | MT_SECURE); 103 } 104 105 int stm32mp_unmap_ddr(void) 106 { 107 return mmap_remove_dynamic_region(STM32MP_DDR_BASE, 108 STM32MP_DDR_MAX_SIZE); 109 } 110 111 int stm32_get_otp_index(const char *otp_name, uint32_t *otp_idx, 112 uint32_t *otp_len) 113 { 114 assert(otp_name != NULL); 115 assert(otp_idx != NULL); 116 117 return dt_find_otp_name(otp_name, otp_idx, otp_len); 118 } 119 120 int stm32_get_otp_value(const char *otp_name, uint32_t *otp_val) 121 { 122 uint32_t otp_idx; 123 124 assert(otp_name != NULL); 125 assert(otp_val != NULL); 126 127 if (stm32_get_otp_index(otp_name, &otp_idx, NULL) != 0) { 128 return -1; 129 } 130 131 if (stm32_get_otp_value_from_idx(otp_idx, otp_val) != 0) { 132 ERROR("BSEC: %s Read Error\n", otp_name); 133 return -1; 134 } 135 136 return 0; 137 } 138 139 int stm32_get_otp_value_from_idx(const uint32_t otp_idx, uint32_t *otp_val) 140 { 141 uint32_t ret = BSEC_NOT_SUPPORTED; 142 143 assert(otp_val != NULL); 144 145 #if defined(IMAGE_BL2) 146 ret = bsec_shadow_read_otp(otp_val, otp_idx); 147 #elif defined(IMAGE_BL32) 148 ret = bsec_read_otp(otp_val, otp_idx); 149 #else 150 #error "Not supported" 151 #endif 152 if (ret != BSEC_OK) { 153 ERROR("BSEC: idx=%u Read Error\n", otp_idx); 154 return -1; 155 } 156 157 return 0; 158 } 159 160 #if defined(IMAGE_BL2) 161 static void reset_uart(uint32_t reset) 162 { 163 int ret; 164 165 ret = stm32mp_reset_assert(reset, RESET_TIMEOUT_US_1MS); 166 if (ret != 0) { 167 panic(); 168 } 169 170 udelay(2); 171 172 ret = stm32mp_reset_deassert(reset, RESET_TIMEOUT_US_1MS); 173 if (ret != 0) { 174 panic(); 175 } 176 177 mdelay(1); 178 } 179 #endif 180 181 static void set_console(uintptr_t base, uint32_t clk_rate) 182 { 183 unsigned int console_flags; 184 185 if (console_stm32_register(base, clk_rate, 186 (uint32_t)STM32MP_UART_BAUDRATE, &console) == 0) { 187 panic(); 188 } 189 190 console_flags = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH | 191 CONSOLE_FLAG_TRANSLATE_CRLF; 192 #if !defined(IMAGE_BL2) && defined(DEBUG) 193 console_flags |= CONSOLE_FLAG_RUNTIME; 194 #endif 195 196 console_set_scope(&console, console_flags); 197 } 198 199 int stm32mp_uart_console_setup(void) 200 { 201 struct dt_node_info dt_uart_info; 202 uint32_t clk_rate = 0U; 203 int result; 204 uint32_t boot_itf __unused; 205 uint32_t boot_instance __unused; 206 207 result = dt_get_stdout_uart_info(&dt_uart_info); 208 209 if ((result <= 0) || 210 (dt_uart_info.status == DT_DISABLED)) { 211 return -ENODEV; 212 } 213 214 #if defined(IMAGE_BL2) 215 if ((dt_uart_info.clock < 0) || 216 (dt_uart_info.reset < 0)) { 217 return -ENODEV; 218 } 219 #endif 220 221 #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2) 222 stm32_get_boot_interface(&boot_itf, &boot_instance); 223 224 if ((boot_itf == BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) && 225 (get_uart_address(boot_instance) == dt_uart_info.base)) { 226 return -EACCES; 227 } 228 #endif 229 230 #if defined(IMAGE_BL2) 231 if (dt_set_stdout_pinctrl() != 0) { 232 return -ENODEV; 233 } 234 235 clk_enable((unsigned long)dt_uart_info.clock); 236 237 reset_uart((uint32_t)dt_uart_info.reset); 238 239 clk_rate = clk_get_rate((unsigned long)dt_uart_info.clock); 240 #endif 241 242 set_console(dt_uart_info.base, clk_rate); 243 244 return 0; 245 } 246 247 #if STM32MP_EARLY_CONSOLE 248 void stm32mp_setup_early_console(void) 249 { 250 #if defined(IMAGE_BL2) || STM32MP_RECONFIGURE_CONSOLE 251 plat_crash_console_init(); 252 #endif 253 set_console(STM32MP_DEBUG_USART_BASE, STM32MP_DEBUG_USART_CLK_FRQ); 254 NOTICE("Early console setup\n"); 255 } 256 #endif /* STM32MP_EARLY_CONSOLE */ 257 258 /***************************************************************************** 259 * plat_is_smccc_feature_available() - This function checks whether SMCCC 260 * feature is availabile for platform. 261 * @fid: SMCCC function id 262 * 263 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and 264 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise. 265 *****************************************************************************/ 266 int32_t plat_is_smccc_feature_available(u_register_t fid) 267 { 268 switch (fid) { 269 case SMCCC_ARCH_SOC_ID: 270 return SMC_ARCH_CALL_SUCCESS; 271 default: 272 return SMC_ARCH_CALL_NOT_SUPPORTED; 273 } 274 } 275 276 /* Get SOC version */ 277 int32_t plat_get_soc_version(void) 278 { 279 uint32_t chip_id = stm32mp_get_chip_dev_id(); 280 uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_ST_BKID, JEDEC_ST_MFID); 281 282 return (int32_t)(manfid | (chip_id & SOC_ID_IMPL_DEF_MASK)); 283 } 284 285 /* Get SOC revision */ 286 int32_t plat_get_soc_revision(void) 287 { 288 return (int32_t)(stm32mp_get_chip_version() & SOC_ID_REV_MASK); 289 } 290 291 void stm32_save_boot_info(boot_api_context_t *boot_context) 292 { 293 uint32_t auth_status; 294 295 assert(boot_context->boot_interface_instance <= (BOOT_INST_MASK >> BOOT_INST_SHIFT)); 296 assert(boot_context->boot_interface_selected <= (BOOT_ITF_MASK >> BOOT_ITF_SHIFT)); 297 assert(boot_context->boot_partition_used_toboot <= (BOOT_PART_MASK >> BOOT_PART_SHIFT)); 298 299 switch (boot_context->auth_status) { 300 case BOOT_API_CTX_AUTH_NO: 301 auth_status = 0x0U; 302 break; 303 304 case BOOT_API_CTX_AUTH_SUCCESS: 305 auth_status = 0x2U; 306 break; 307 308 case BOOT_API_CTX_AUTH_FAILED: 309 default: 310 auth_status = 0x1U; 311 break; 312 } 313 314 clk_enable(TAMP_BKP_REG_CLK); 315 316 mmio_clrsetbits_32(stm32_get_bkpr_boot_mode_addr(), 317 BOOT_ITF_MASK | BOOT_INST_MASK | BOOT_PART_MASK | BOOT_AUTH_MASK, 318 (boot_context->boot_interface_instance << BOOT_INST_SHIFT) | 319 (boot_context->boot_interface_selected << BOOT_ITF_SHIFT) | 320 (boot_context->boot_partition_used_toboot << BOOT_PART_SHIFT) | 321 (auth_status << BOOT_AUTH_SHIFT)); 322 323 clk_disable(TAMP_BKP_REG_CLK); 324 } 325 326 void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance) 327 { 328 static uint32_t itf; 329 330 if (itf == 0U) { 331 clk_enable(TAMP_BKP_REG_CLK); 332 333 itf = mmio_read_32(stm32_get_bkpr_boot_mode_addr()) & 334 (BOOT_ITF_MASK | BOOT_INST_MASK); 335 336 clk_disable(TAMP_BKP_REG_CLK); 337 } 338 339 *interface = (itf & BOOT_ITF_MASK) >> BOOT_ITF_SHIFT; 340 *instance = (itf & BOOT_INST_MASK) >> BOOT_INST_SHIFT; 341 } 342