1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <drivers/delay_timer.h> 13 #include <drivers/st/stm32_console.h> 14 #include <drivers/st/stm32mp_clkfunc.h> 15 #include <drivers/st/stm32mp_reset.h> 16 #include <lib/smccc.h> 17 #include <lib/xlat_tables/xlat_tables_v2.h> 18 #include <plat/common/platform.h> 19 #include <services/arm_arch_svc.h> 20 21 #include <platform_def.h> 22 23 #define HEADER_VERSION_MAJOR_MASK GENMASK(23, 16) 24 #define RESET_TIMEOUT_US_1MS 1000U 25 26 static console_t console; 27 28 uintptr_t plat_get_ns_image_entrypoint(void) 29 { 30 return BL33_BASE; 31 } 32 33 unsigned int plat_get_syscnt_freq2(void) 34 { 35 return read_cntfrq_el0(); 36 } 37 38 static uintptr_t boot_ctx_address; 39 static uint16_t boot_itf_selected; 40 41 void stm32mp_save_boot_ctx_address(uintptr_t address) 42 { 43 boot_api_context_t *boot_context = (boot_api_context_t *)address; 44 45 boot_ctx_address = address; 46 boot_itf_selected = boot_context->boot_interface_selected; 47 } 48 49 uintptr_t stm32mp_get_boot_ctx_address(void) 50 { 51 return boot_ctx_address; 52 } 53 54 uint16_t stm32mp_get_boot_itf_selected(void) 55 { 56 return boot_itf_selected; 57 } 58 59 uintptr_t stm32mp_ddrctrl_base(void) 60 { 61 return DDRCTRL_BASE; 62 } 63 64 uintptr_t stm32mp_ddrphyc_base(void) 65 { 66 return DDRPHYC_BASE; 67 } 68 69 uintptr_t stm32mp_pwr_base(void) 70 { 71 return PWR_BASE; 72 } 73 74 uintptr_t stm32mp_rcc_base(void) 75 { 76 return RCC_BASE; 77 } 78 79 bool stm32mp_lock_available(void) 80 { 81 const uint32_t c_m_bits = SCTLR_M_BIT | SCTLR_C_BIT; 82 83 /* The spinlocks are used only when MMU and data cache are enabled */ 84 return (read_sctlr() & c_m_bits) == c_m_bits; 85 } 86 87 #if STM32MP_USE_STM32IMAGE 88 int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer) 89 { 90 uint32_t i; 91 uint32_t img_checksum = 0U; 92 93 /* 94 * Check header/payload validity: 95 * - Header magic 96 * - Header version 97 * - Payload checksum 98 */ 99 if (header->magic != BOOT_API_IMAGE_HEADER_MAGIC_NB) { 100 ERROR("Header magic\n"); 101 return -EINVAL; 102 } 103 104 if ((header->header_version & HEADER_VERSION_MAJOR_MASK) != 105 (BOOT_API_HEADER_VERSION & HEADER_VERSION_MAJOR_MASK)) { 106 ERROR("Header version\n"); 107 return -EINVAL; 108 } 109 110 for (i = 0U; i < header->image_length; i++) { 111 img_checksum += *(uint8_t *)(buffer + i); 112 } 113 114 if (header->payload_checksum != img_checksum) { 115 ERROR("Checksum: 0x%x (awaited: 0x%x)\n", img_checksum, 116 header->payload_checksum); 117 return -EINVAL; 118 } 119 120 return 0; 121 } 122 #endif /* STM32MP_USE_STM32IMAGE */ 123 124 int stm32mp_map_ddr_non_cacheable(void) 125 { 126 return mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, 127 STM32MP_DDR_MAX_SIZE, 128 MT_NON_CACHEABLE | MT_RW | MT_SECURE); 129 } 130 131 int stm32mp_unmap_ddr(void) 132 { 133 return mmap_remove_dynamic_region(STM32MP_DDR_BASE, 134 STM32MP_DDR_MAX_SIZE); 135 } 136 137 #if defined(IMAGE_BL2) 138 static void reset_uart(uint32_t reset) 139 { 140 int ret; 141 142 ret = stm32mp_reset_assert(reset, RESET_TIMEOUT_US_1MS); 143 if (ret != 0) { 144 panic(); 145 } 146 147 udelay(2); 148 149 ret = stm32mp_reset_deassert(reset, RESET_TIMEOUT_US_1MS); 150 if (ret != 0) { 151 panic(); 152 } 153 154 mdelay(1); 155 } 156 #endif 157 158 int stm32mp_uart_console_setup(void) 159 { 160 struct dt_node_info dt_uart_info; 161 unsigned int console_flags; 162 uint32_t clk_rate; 163 int result; 164 uint32_t boot_itf __unused; 165 uint32_t boot_instance __unused; 166 167 result = dt_get_stdout_uart_info(&dt_uart_info); 168 169 if ((result <= 0) || 170 (dt_uart_info.status == DT_DISABLED) || 171 (dt_uart_info.clock < 0) || 172 (dt_uart_info.reset < 0)) { 173 return -ENODEV; 174 } 175 176 #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2) 177 stm32_get_boot_interface(&boot_itf, &boot_instance); 178 179 if ((boot_itf == BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) && 180 (get_uart_address(boot_instance) == dt_uart_info.base)) { 181 return -EACCES; 182 } 183 #endif 184 185 #if defined(IMAGE_BL2) 186 if (dt_set_stdout_pinctrl() != 0) { 187 return -ENODEV; 188 } 189 #endif 190 191 stm32mp_clk_enable((unsigned long)dt_uart_info.clock); 192 193 #if defined(IMAGE_BL2) 194 reset_uart((uint32_t)dt_uart_info.reset); 195 #endif 196 197 clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock); 198 199 if (console_stm32_register(dt_uart_info.base, clk_rate, 200 STM32MP_UART_BAUDRATE, &console) == 0) { 201 panic(); 202 } 203 204 console_flags = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH | 205 CONSOLE_FLAG_TRANSLATE_CRLF; 206 #if !defined(IMAGE_BL2) && defined(DEBUG) 207 console_flags |= CONSOLE_FLAG_RUNTIME; 208 #endif 209 console_set_scope(&console, console_flags); 210 211 return 0; 212 } 213 214 /***************************************************************************** 215 * plat_is_smccc_feature_available() - This function checks whether SMCCC 216 * feature is availabile for platform. 217 * @fid: SMCCC function id 218 * 219 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and 220 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise. 221 *****************************************************************************/ 222 int32_t plat_is_smccc_feature_available(u_register_t fid) 223 { 224 switch (fid) { 225 case SMCCC_ARCH_SOC_ID: 226 return SMC_ARCH_CALL_SUCCESS; 227 default: 228 return SMC_ARCH_CALL_NOT_SUPPORTED; 229 } 230 } 231 232 /* Get SOC version */ 233 int32_t plat_get_soc_version(void) 234 { 235 uint32_t chip_id = stm32mp_get_chip_dev_id(); 236 uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_ST_BKID, JEDEC_ST_MFID); 237 238 return (int32_t)(manfid | (chip_id & SOC_ID_IMPL_DEF_MASK)); 239 } 240 241 /* Get SOC revision */ 242 int32_t plat_get_soc_revision(void) 243 { 244 return (int32_t)(stm32mp_get_chip_version() & SOC_ID_REV_MASK); 245 } 246