1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <drivers/st/stm32mp_clkfunc.h> 15 #include <plat/common/platform.h> 16 17 uintptr_t plat_get_ns_image_entrypoint(void) 18 { 19 return BL33_BASE; 20 } 21 22 unsigned int plat_get_syscnt_freq2(void) 23 { 24 return read_cntfrq_el0(); 25 } 26 27 static uintptr_t boot_ctx_address; 28 29 void stm32mp_save_boot_ctx_address(uintptr_t address) 30 { 31 boot_ctx_address = address; 32 } 33 34 uintptr_t stm32mp_get_boot_ctx_address(void) 35 { 36 return boot_ctx_address; 37 } 38 39 uintptr_t stm32mp_ddrctrl_base(void) 40 { 41 static uintptr_t ddrctrl_base; 42 43 if (ddrctrl_base == 0) { 44 ddrctrl_base = dt_get_ddrctrl_base(); 45 46 assert(ddrctrl_base == DDRCTRL_BASE); 47 } 48 49 return ddrctrl_base; 50 } 51 52 uintptr_t stm32mp_ddrphyc_base(void) 53 { 54 static uintptr_t ddrphyc_base; 55 56 if (ddrphyc_base == 0) { 57 ddrphyc_base = dt_get_ddrphyc_base(); 58 59 assert(ddrphyc_base == DDRPHYC_BASE); 60 } 61 62 return ddrphyc_base; 63 } 64 65 uintptr_t stm32mp_pwr_base(void) 66 { 67 static uintptr_t pwr_base; 68 69 if (pwr_base == 0) { 70 pwr_base = dt_get_pwr_base(); 71 72 assert(pwr_base == PWR_BASE); 73 } 74 75 return pwr_base; 76 } 77 78 uintptr_t stm32mp_rcc_base(void) 79 { 80 static uintptr_t rcc_base; 81 82 if (rcc_base == 0) { 83 rcc_base = fdt_rcc_read_addr(); 84 85 assert(rcc_base == RCC_BASE); 86 } 87 88 return rcc_base; 89 } 90 91 bool stm32mp_lock_available(void) 92 { 93 const uint32_t c_m_bits = SCTLR_M_BIT | SCTLR_C_BIT; 94 95 /* The spinlocks are used only when MMU and data cache are enabled */ 96 return (read_sctlr() & c_m_bits) == c_m_bits; 97 } 98 99 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) 100 { 101 if (bank == GPIO_BANK_Z) { 102 return GPIOZ_BASE; 103 } 104 105 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 106 107 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); 108 } 109 110 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) 111 { 112 if (bank == GPIO_BANK_Z) { 113 return 0; 114 } 115 116 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 117 118 return bank * GPIO_BANK_OFFSET; 119 } 120 121 int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer) 122 { 123 uint32_t i; 124 uint32_t img_checksum = 0U; 125 126 /* 127 * Check header/payload validity: 128 * - Header magic 129 * - Header version 130 * - Payload checksum 131 */ 132 if (header->magic != BOOT_API_IMAGE_HEADER_MAGIC_NB) { 133 ERROR("Header magic\n"); 134 return -EINVAL; 135 } 136 137 if (header->header_version != BOOT_API_HEADER_VERSION) { 138 ERROR("Header version\n"); 139 return -EINVAL; 140 } 141 142 for (i = 0U; i < header->image_length; i++) { 143 img_checksum += *(uint8_t *)(buffer + i); 144 } 145 146 if (header->payload_checksum != img_checksum) { 147 ERROR("Checksum: 0x%x (awaited: 0x%x)\n", img_checksum, 148 header->payload_checksum); 149 return -EINVAL; 150 } 151 152 return 0; 153 } 154