1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <drivers/clk.h> 13 #include <drivers/delay_timer.h> 14 #include <drivers/st/stm32_console.h> 15 #include <drivers/st/stm32mp_clkfunc.h> 16 #include <drivers/st/stm32mp_reset.h> 17 #include <lib/smccc.h> 18 #include <lib/xlat_tables/xlat_tables_v2.h> 19 #include <plat/common/platform.h> 20 #include <services/arm_arch_svc.h> 21 22 #include <platform_def.h> 23 24 #define HEADER_VERSION_MAJOR_MASK GENMASK(23, 16) 25 #define RESET_TIMEOUT_US_1MS 1000U 26 27 static console_t console; 28 29 uintptr_t plat_get_ns_image_entrypoint(void) 30 { 31 return BL33_BASE; 32 } 33 34 unsigned int plat_get_syscnt_freq2(void) 35 { 36 return read_cntfrq_el0(); 37 } 38 39 static uintptr_t boot_ctx_address; 40 static uint16_t boot_itf_selected; 41 42 void stm32mp_save_boot_ctx_address(uintptr_t address) 43 { 44 boot_api_context_t *boot_context = (boot_api_context_t *)address; 45 46 boot_ctx_address = address; 47 boot_itf_selected = boot_context->boot_interface_selected; 48 } 49 50 uintptr_t stm32mp_get_boot_ctx_address(void) 51 { 52 return boot_ctx_address; 53 } 54 55 uint16_t stm32mp_get_boot_itf_selected(void) 56 { 57 return boot_itf_selected; 58 } 59 60 uintptr_t stm32mp_ddrctrl_base(void) 61 { 62 return DDRCTRL_BASE; 63 } 64 65 uintptr_t stm32mp_ddrphyc_base(void) 66 { 67 return DDRPHYC_BASE; 68 } 69 70 uintptr_t stm32mp_pwr_base(void) 71 { 72 return PWR_BASE; 73 } 74 75 uintptr_t stm32mp_rcc_base(void) 76 { 77 return RCC_BASE; 78 } 79 80 bool stm32mp_lock_available(void) 81 { 82 const uint32_t c_m_bits = SCTLR_M_BIT | SCTLR_C_BIT; 83 84 /* The spinlocks are used only when MMU and data cache are enabled */ 85 return (read_sctlr() & c_m_bits) == c_m_bits; 86 } 87 88 #if STM32MP_USE_STM32IMAGE 89 int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer) 90 { 91 uint32_t i; 92 uint32_t img_checksum = 0U; 93 94 /* 95 * Check header/payload validity: 96 * - Header magic 97 * - Header version 98 * - Payload checksum 99 */ 100 if (header->magic != BOOT_API_IMAGE_HEADER_MAGIC_NB) { 101 ERROR("Header magic\n"); 102 return -EINVAL; 103 } 104 105 if ((header->header_version & HEADER_VERSION_MAJOR_MASK) != 106 (BOOT_API_HEADER_VERSION & HEADER_VERSION_MAJOR_MASK)) { 107 ERROR("Header version\n"); 108 return -EINVAL; 109 } 110 111 for (i = 0U; i < header->image_length; i++) { 112 img_checksum += *(uint8_t *)(buffer + i); 113 } 114 115 if (header->payload_checksum != img_checksum) { 116 ERROR("Checksum: 0x%x (awaited: 0x%x)\n", img_checksum, 117 header->payload_checksum); 118 return -EINVAL; 119 } 120 121 return 0; 122 } 123 #endif /* STM32MP_USE_STM32IMAGE */ 124 125 int stm32mp_map_ddr_non_cacheable(void) 126 { 127 return mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, 128 STM32MP_DDR_MAX_SIZE, 129 MT_NON_CACHEABLE | MT_RW | MT_SECURE); 130 } 131 132 int stm32mp_unmap_ddr(void) 133 { 134 return mmap_remove_dynamic_region(STM32MP_DDR_BASE, 135 STM32MP_DDR_MAX_SIZE); 136 } 137 138 #if defined(IMAGE_BL2) 139 static void reset_uart(uint32_t reset) 140 { 141 int ret; 142 143 ret = stm32mp_reset_assert(reset, RESET_TIMEOUT_US_1MS); 144 if (ret != 0) { 145 panic(); 146 } 147 148 udelay(2); 149 150 ret = stm32mp_reset_deassert(reset, RESET_TIMEOUT_US_1MS); 151 if (ret != 0) { 152 panic(); 153 } 154 155 mdelay(1); 156 } 157 #endif 158 159 int stm32mp_uart_console_setup(void) 160 { 161 struct dt_node_info dt_uart_info; 162 unsigned int console_flags; 163 uint32_t clk_rate; 164 int result; 165 uint32_t boot_itf __unused; 166 uint32_t boot_instance __unused; 167 168 result = dt_get_stdout_uart_info(&dt_uart_info); 169 170 if ((result <= 0) || 171 (dt_uart_info.status == DT_DISABLED) || 172 (dt_uart_info.clock < 0) || 173 (dt_uart_info.reset < 0)) { 174 return -ENODEV; 175 } 176 177 #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2) 178 stm32_get_boot_interface(&boot_itf, &boot_instance); 179 180 if ((boot_itf == BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) && 181 (get_uart_address(boot_instance) == dt_uart_info.base)) { 182 return -EACCES; 183 } 184 #endif 185 186 #if defined(IMAGE_BL2) 187 if (dt_set_stdout_pinctrl() != 0) { 188 return -ENODEV; 189 } 190 #endif 191 192 clk_enable((unsigned long)dt_uart_info.clock); 193 194 #if defined(IMAGE_BL2) 195 reset_uart((uint32_t)dt_uart_info.reset); 196 #endif 197 198 clk_rate = clk_get_rate((unsigned long)dt_uart_info.clock); 199 200 if (console_stm32_register(dt_uart_info.base, clk_rate, 201 STM32MP_UART_BAUDRATE, &console) == 0) { 202 panic(); 203 } 204 205 console_flags = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH | 206 CONSOLE_FLAG_TRANSLATE_CRLF; 207 #if !defined(IMAGE_BL2) && defined(DEBUG) 208 console_flags |= CONSOLE_FLAG_RUNTIME; 209 #endif 210 console_set_scope(&console, console_flags); 211 212 return 0; 213 } 214 215 /***************************************************************************** 216 * plat_is_smccc_feature_available() - This function checks whether SMCCC 217 * feature is availabile for platform. 218 * @fid: SMCCC function id 219 * 220 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and 221 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise. 222 *****************************************************************************/ 223 int32_t plat_is_smccc_feature_available(u_register_t fid) 224 { 225 switch (fid) { 226 case SMCCC_ARCH_SOC_ID: 227 return SMC_ARCH_CALL_SUCCESS; 228 default: 229 return SMC_ARCH_CALL_NOT_SUPPORTED; 230 } 231 } 232 233 /* Get SOC version */ 234 int32_t plat_get_soc_version(void) 235 { 236 uint32_t chip_id = stm32mp_get_chip_dev_id(); 237 uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_ST_BKID, JEDEC_ST_MFID); 238 239 return (int32_t)(manfid | (chip_id & SOC_ID_IMPL_DEF_MASK)); 240 } 241 242 /* Get SOC revision */ 243 int32_t plat_get_soc_revision(void) 244 { 245 return (int32_t)(stm32mp_get_chip_version() & SOC_ID_REV_MASK); 246 } 247