1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <drivers/st/stm32mp_clkfunc.h> 15 #include <lib/smccc.h> 16 #include <lib/xlat_tables/xlat_tables_v2.h> 17 #include <plat/common/platform.h> 18 #include <services/arm_arch_svc.h> 19 20 uintptr_t plat_get_ns_image_entrypoint(void) 21 { 22 return BL33_BASE; 23 } 24 25 unsigned int plat_get_syscnt_freq2(void) 26 { 27 return read_cntfrq_el0(); 28 } 29 30 static uintptr_t boot_ctx_address; 31 static uint16_t boot_itf_selected; 32 33 void stm32mp_save_boot_ctx_address(uintptr_t address) 34 { 35 boot_api_context_t *boot_context = (boot_api_context_t *)address; 36 37 boot_ctx_address = address; 38 boot_itf_selected = boot_context->boot_interface_selected; 39 } 40 41 uintptr_t stm32mp_get_boot_ctx_address(void) 42 { 43 return boot_ctx_address; 44 } 45 46 uint16_t stm32mp_get_boot_itf_selected(void) 47 { 48 return boot_itf_selected; 49 } 50 51 uintptr_t stm32mp_ddrctrl_base(void) 52 { 53 return DDRCTRL_BASE; 54 } 55 56 uintptr_t stm32mp_ddrphyc_base(void) 57 { 58 return DDRPHYC_BASE; 59 } 60 61 uintptr_t stm32mp_pwr_base(void) 62 { 63 return PWR_BASE; 64 } 65 66 uintptr_t stm32mp_rcc_base(void) 67 { 68 return RCC_BASE; 69 } 70 71 bool stm32mp_lock_available(void) 72 { 73 const uint32_t c_m_bits = SCTLR_M_BIT | SCTLR_C_BIT; 74 75 /* The spinlocks are used only when MMU and data cache are enabled */ 76 return (read_sctlr() & c_m_bits) == c_m_bits; 77 } 78 79 int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer) 80 { 81 uint32_t i; 82 uint32_t img_checksum = 0U; 83 84 /* 85 * Check header/payload validity: 86 * - Header magic 87 * - Header version 88 * - Payload checksum 89 */ 90 if (header->magic != BOOT_API_IMAGE_HEADER_MAGIC_NB) { 91 ERROR("Header magic\n"); 92 return -EINVAL; 93 } 94 95 if (header->header_version != BOOT_API_HEADER_VERSION) { 96 ERROR("Header version\n"); 97 return -EINVAL; 98 } 99 100 for (i = 0U; i < header->image_length; i++) { 101 img_checksum += *(uint8_t *)(buffer + i); 102 } 103 104 if (header->payload_checksum != img_checksum) { 105 ERROR("Checksum: 0x%x (awaited: 0x%x)\n", img_checksum, 106 header->payload_checksum); 107 return -EINVAL; 108 } 109 110 return 0; 111 } 112 113 int stm32mp_map_ddr_non_cacheable(void) 114 { 115 return mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, 116 STM32MP_DDR_MAX_SIZE, 117 MT_NON_CACHEABLE | MT_RW | MT_SECURE); 118 } 119 120 int stm32mp_unmap_ddr(void) 121 { 122 return mmap_remove_dynamic_region(STM32MP_DDR_BASE, 123 STM32MP_DDR_MAX_SIZE); 124 } 125 126 /***************************************************************************** 127 * plat_is_smccc_feature_available() - This function checks whether SMCCC 128 * feature is availabile for platform. 129 * @fid: SMCCC function id 130 * 131 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and 132 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise. 133 *****************************************************************************/ 134 int32_t plat_is_smccc_feature_available(u_register_t fid) 135 { 136 switch (fid) { 137 case SMCCC_ARCH_SOC_ID: 138 return SMC_ARCH_CALL_SUCCESS; 139 default: 140 return SMC_ARCH_CALL_NOT_SUPPORTED; 141 } 142 } 143 144 /* Get SOC version */ 145 int32_t plat_get_soc_version(void) 146 { 147 uint32_t chip_id = stm32mp_get_chip_dev_id(); 148 uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_ST_BKID, JEDEC_ST_MFID); 149 150 return (int32_t)(manfid | (chip_id & SOC_ID_IMPL_DEF_MASK)); 151 } 152 153 /* Get SOC revision */ 154 int32_t plat_get_soc_revision(void) 155 { 156 return (int32_t)(stm32mp_get_chip_version() & SOC_ID_REV_MASK); 157 } 158