1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <drivers/st/stm32mp_clkfunc.h> 15 #include <lib/smccc.h> 16 #include <lib/xlat_tables/xlat_tables_v2.h> 17 #include <plat/common/platform.h> 18 #include <services/arm_arch_svc.h> 19 20 uintptr_t plat_get_ns_image_entrypoint(void) 21 { 22 return BL33_BASE; 23 } 24 25 unsigned int plat_get_syscnt_freq2(void) 26 { 27 return read_cntfrq_el0(); 28 } 29 30 static uintptr_t boot_ctx_address; 31 32 void stm32mp_save_boot_ctx_address(uintptr_t address) 33 { 34 boot_ctx_address = address; 35 } 36 37 uintptr_t stm32mp_get_boot_ctx_address(void) 38 { 39 return boot_ctx_address; 40 } 41 42 uintptr_t stm32mp_ddrctrl_base(void) 43 { 44 return DDRCTRL_BASE; 45 } 46 47 uintptr_t stm32mp_ddrphyc_base(void) 48 { 49 return DDRPHYC_BASE; 50 } 51 52 uintptr_t stm32mp_pwr_base(void) 53 { 54 return PWR_BASE; 55 } 56 57 uintptr_t stm32mp_rcc_base(void) 58 { 59 return RCC_BASE; 60 } 61 62 bool stm32mp_lock_available(void) 63 { 64 const uint32_t c_m_bits = SCTLR_M_BIT | SCTLR_C_BIT; 65 66 /* The spinlocks are used only when MMU and data cache are enabled */ 67 return (read_sctlr() & c_m_bits) == c_m_bits; 68 } 69 70 int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer) 71 { 72 uint32_t i; 73 uint32_t img_checksum = 0U; 74 75 /* 76 * Check header/payload validity: 77 * - Header magic 78 * - Header version 79 * - Payload checksum 80 */ 81 if (header->magic != BOOT_API_IMAGE_HEADER_MAGIC_NB) { 82 ERROR("Header magic\n"); 83 return -EINVAL; 84 } 85 86 if (header->header_version != BOOT_API_HEADER_VERSION) { 87 ERROR("Header version\n"); 88 return -EINVAL; 89 } 90 91 for (i = 0U; i < header->image_length; i++) { 92 img_checksum += *(uint8_t *)(buffer + i); 93 } 94 95 if (header->payload_checksum != img_checksum) { 96 ERROR("Checksum: 0x%x (awaited: 0x%x)\n", img_checksum, 97 header->payload_checksum); 98 return -EINVAL; 99 } 100 101 return 0; 102 } 103 104 int stm32mp_map_ddr_non_cacheable(void) 105 { 106 return mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, 107 STM32MP_DDR_MAX_SIZE, 108 MT_NON_CACHEABLE | MT_RW | MT_NS); 109 } 110 111 int stm32mp_unmap_ddr(void) 112 { 113 return mmap_remove_dynamic_region(STM32MP_DDR_BASE, 114 STM32MP_DDR_MAX_SIZE); 115 } 116 117 /***************************************************************************** 118 * plat_is_smccc_feature_available() - This function checks whether SMCCC 119 * feature is availabile for platform. 120 * @fid: SMCCC function id 121 * 122 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and 123 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise. 124 *****************************************************************************/ 125 int32_t plat_is_smccc_feature_available(u_register_t fid) 126 { 127 switch (fid) { 128 case SMCCC_ARCH_SOC_ID: 129 return SMC_ARCH_CALL_SUCCESS; 130 default: 131 return SMC_ARCH_CALL_NOT_SUPPORTED; 132 } 133 } 134 135 /* Get SOC version */ 136 int32_t plat_get_soc_version(void) 137 { 138 uint32_t chip_id = stm32mp_get_chip_dev_id(); 139 uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_ST_BKID, JEDEC_ST_MFID); 140 141 return (int32_t)(manfid | (chip_id & SOC_ID_IMPL_DEF_MASK)); 142 } 143 144 /* Get SOC revision */ 145 int32_t plat_get_soc_revision(void) 146 { 147 return (int32_t)(stm32mp_get_chip_version() & SOC_ID_REV_MASK); 148 } 149