147cf5d3fSEtienne Carriere /* 247cf5d3fSEtienne Carriere * Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved 347cf5d3fSEtienne Carriere * 447cf5d3fSEtienne Carriere * SPDX-License-Identifier: BSD-3-Clause 547cf5d3fSEtienne Carriere */ 647cf5d3fSEtienne Carriere 747cf5d3fSEtienne Carriere #ifndef STM32MP_SHARED_RESOURCES_H 847cf5d3fSEtienne Carriere #define STM32MP_SHARED_RESOURCES_H 947cf5d3fSEtienne Carriere 1047cf5d3fSEtienne Carriere #include <stdbool.h> 110651b5b7SEtienne Carriere #include <stdint.h> 1247cf5d3fSEtienne Carriere 1368450c94SEtienne Carriere #ifdef STM32MP_SHARED_RESOURCES 1468450c94SEtienne Carriere enum stm32mp_shres; 1568450c94SEtienne Carriere 1647cf5d3fSEtienne Carriere /* Return true if @clock_id is shared by secure and non-secure worlds */ 1747cf5d3fSEtienne Carriere bool stm32mp_nsec_can_access_clock(unsigned long clock_id); 1847cf5d3fSEtienne Carriere 1947cf5d3fSEtienne Carriere /* Return true if and only if @reset_id relates to a non-secure peripheral */ 2047cf5d3fSEtienne Carriere bool stm32mp_nsec_can_access_reset(unsigned int reset_id); 2147cf5d3fSEtienne Carriere 2268450c94SEtienne Carriere /* Register a shared resource assigned to the secure world */ 2368450c94SEtienne Carriere void stm32mp_register_secure_periph(enum stm32mp_shres id); 2468450c94SEtienne Carriere 2568450c94SEtienne Carriere /* Register a shared resource assigned to the non-secure world */ 2668450c94SEtienne Carriere void stm32mp_register_non_secure_periph(enum stm32mp_shres id); 2768450c94SEtienne Carriere 280651b5b7SEtienne Carriere /* Register a peripheral as secure or non-secure based on IO base address */ 290651b5b7SEtienne Carriere void stm32mp_register_secure_periph_iomem(uintptr_t base); 300651b5b7SEtienne Carriere void stm32mp_register_non_secure_periph_iomem(uintptr_t base); 310651b5b7SEtienne Carriere 32*ec8f4212SEtienne Carriere /* Register a GPIO as secure or non-secure based on its bank and pin numbers */ 33*ec8f4212SEtienne Carriere void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin); 34*ec8f4212SEtienne Carriere void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin); 35*ec8f4212SEtienne Carriere 365f038ac6SEtienne Carriere /* Consolidate peripheral states and lock against new peripheral registering */ 375f038ac6SEtienne Carriere void stm32mp_lock_periph_registering(void); 380651b5b7SEtienne Carriere #else 390651b5b7SEtienne Carriere static inline void stm32mp_register_secure_periph_iomem(uintptr_t base __unused) 400651b5b7SEtienne Carriere { 410651b5b7SEtienne Carriere } 420651b5b7SEtienne Carriere 430651b5b7SEtienne Carriere static inline 440651b5b7SEtienne Carriere void stm32mp_register_non_secure_periph_iomem(uintptr_t base __unused) 450651b5b7SEtienne Carriere { 460651b5b7SEtienne Carriere } 47*ec8f4212SEtienne Carriere 48*ec8f4212SEtienne Carriere static inline void stm32mp_register_secure_gpio(unsigned int bank __unused, 49*ec8f4212SEtienne Carriere unsigned int pin __unused) 50*ec8f4212SEtienne Carriere { 51*ec8f4212SEtienne Carriere } 52*ec8f4212SEtienne Carriere 53*ec8f4212SEtienne Carriere static inline void stm32mp_register_non_secure_gpio(unsigned int bank __unused, 54*ec8f4212SEtienne Carriere unsigned int pin __unused) 55*ec8f4212SEtienne Carriere { 56*ec8f4212SEtienne Carriere } 5768450c94SEtienne Carriere #endif /* STM32MP_SHARED_RESOURCES */ 5847cf5d3fSEtienne Carriere #endif /* STM32MP_SHARED_RESOURCES_H */ 59