xref: /rk3399_ARM-atf/plat/st/common/include/stm32mp_common.h (revision dec286dd7d7b1aae486a05069a80b8791ab0ba55)
1 /*
2  * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
3  * Copyright (c) 2018-2019, Linaro Limited
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef STM32MP_COMMON_H
9 #define STM32MP_COMMON_H
10 
11 #include <stdbool.h>
12 
13 #include <arch_helpers.h>
14 
15 /* Functions to save and get boot context address given by ROM code */
16 void stm32mp_save_boot_ctx_address(uintptr_t address);
17 uintptr_t stm32mp_get_boot_ctx_address(void);
18 
19 /* Return the base address of the DDR controller */
20 uintptr_t stm32mp_ddrctrl_base(void);
21 
22 /* Return the base address of the DDR PHY */
23 uintptr_t stm32mp_ddrphyc_base(void);
24 
25 /* Return the base address of the PWR peripheral */
26 uintptr_t stm32mp_pwr_base(void);
27 
28 /* Return the base address of the RCC peripheral */
29 uintptr_t stm32mp_rcc_base(void);
30 
31 /* Get IWDG platform instance ID from peripheral IO memory base address */
32 uint32_t stm32_iwdg_get_instance(uintptr_t base);
33 
34 /* Return bitflag mask for expected IWDG configuration from OTP content */
35 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst);
36 
37 #if defined(IMAGE_BL2)
38 /* Update OTP shadow registers with IWDG configuration from device tree */
39 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags);
40 #endif
41 
42 /*
43  * Platform util functions for the GPIO driver
44  * @bank: Target GPIO bank ID as per DT bindings
45  *
46  * Platform shall implement these functions to provide to stm32_gpio
47  * driver the resource reference for a target GPIO bank. That are
48  * memory mapped interface base address, interface offset (see below)
49  * and clock identifier.
50  *
51  * stm32_get_gpio_bank_offset() returns a bank offset that is used to
52  * check DT configuration matches platform implementation of the banks
53  * description.
54  */
55 uintptr_t stm32_get_gpio_bank_base(unsigned int bank);
56 unsigned long stm32_get_gpio_bank_clock(unsigned int bank);
57 uint32_t stm32_get_gpio_bank_offset(unsigned int bank);
58 
59 /* Print CPU information */
60 void stm32mp_print_cpuinfo(void);
61 
62 /*
63  * Util for clock gating and to get clock rate for stm32 and platform drivers
64  * @id: Target clock ID, ID used in clock DT bindings
65  */
66 bool stm32mp_clk_is_enabled(unsigned long id);
67 void stm32mp_clk_enable(unsigned long id);
68 void stm32mp_clk_disable(unsigned long id);
69 unsigned long stm32mp_clk_get_rate(unsigned long id);
70 
71 /* Initialise the IO layer and register platform IO devices */
72 void stm32mp_io_setup(void);
73 
74 static inline uint64_t arm_cnt_us2cnt(uint32_t us)
75 {
76 	return ((uint64_t)us * (uint64_t)read_cntfrq()) / 1000000ULL;
77 }
78 
79 static inline uint64_t timeout_init_us(uint32_t us)
80 {
81 	return read_cntpct_el0() + arm_cnt_us2cnt(us);
82 }
83 
84 static inline bool timeout_elapsed(uint64_t expire)
85 {
86 	return read_cntpct_el0() > expire;
87 }
88 
89 #endif /* STM32MP_COMMON_H */
90