1 /* 2 * Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP_COMMON_H 8 #define STM32MP_COMMON_H 9 10 #include <stdbool.h> 11 12 #include <platform_def.h> 13 14 #define JEDEC_ST_BKID U(0x0) 15 #define JEDEC_ST_MFID U(0x20) 16 17 /* Functions to save and get boot context address given by ROM code */ 18 void stm32mp_save_boot_ctx_address(uintptr_t address); 19 uintptr_t stm32mp_get_boot_ctx_address(void); 20 21 bool stm32mp_is_single_core(void); 22 bool stm32mp_is_closed_device(void); 23 24 /* Return the base address of the DDR controller */ 25 uintptr_t stm32mp_ddrctrl_base(void); 26 27 /* Return the base address of the DDR PHY */ 28 uintptr_t stm32mp_ddrphyc_base(void); 29 30 /* Return the base address of the PWR peripheral */ 31 uintptr_t stm32mp_pwr_base(void); 32 33 /* Return the base address of the RCC peripheral */ 34 uintptr_t stm32mp_rcc_base(void); 35 36 /* Check MMU status to allow spinlock use */ 37 bool stm32mp_lock_available(void); 38 39 /* Get IWDG platform instance ID from peripheral IO memory base address */ 40 uint32_t stm32_iwdg_get_instance(uintptr_t base); 41 42 /* Return bitflag mask for expected IWDG configuration from OTP content */ 43 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst); 44 45 #if defined(IMAGE_BL2) 46 /* Update OTP shadow registers with IWDG configuration from device tree */ 47 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags); 48 #endif 49 50 /* 51 * Platform util functions for the GPIO driver 52 * @bank: Target GPIO bank ID as per DT bindings 53 * 54 * Platform shall implement these functions to provide to stm32_gpio 55 * driver the resource reference for a target GPIO bank. That are 56 * memory mapped interface base address, interface offset (see below) 57 * and clock identifier. 58 * 59 * stm32_get_gpio_bank_offset() returns a bank offset that is used to 60 * check DT configuration matches platform implementation of the banks 61 * description. 62 */ 63 uintptr_t stm32_get_gpio_bank_base(unsigned int bank); 64 unsigned long stm32_get_gpio_bank_clock(unsigned int bank); 65 uint32_t stm32_get_gpio_bank_offset(unsigned int bank); 66 67 /* Return node offset for target GPIO bank ID @bank or a FDT error code */ 68 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank); 69 70 /* Get the chip revision */ 71 uint32_t stm32mp_get_chip_version(void); 72 /* Get the chip device ID */ 73 uint32_t stm32mp_get_chip_dev_id(void); 74 75 /* Get SOC name */ 76 #define STM32_SOC_NAME_SIZE 20 77 void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]); 78 79 /* Print CPU information */ 80 void stm32mp_print_cpuinfo(void); 81 82 /* Print board information */ 83 void stm32mp_print_boardinfo(void); 84 85 /* 86 * Util for clock gating and to get clock rate for stm32 and platform drivers 87 * @id: Target clock ID, ID used in clock DT bindings 88 */ 89 bool stm32mp_clk_is_enabled(unsigned long id); 90 void stm32mp_clk_enable(unsigned long id); 91 void stm32mp_clk_disable(unsigned long id); 92 unsigned long stm32mp_clk_get_rate(unsigned long id); 93 94 /* Initialise the IO layer and register platform IO devices */ 95 void stm32mp_io_setup(void); 96 97 /* 98 * Check that the STM32 header of a .stm32 binary image is valid 99 * @param header: pointer to the stm32 image header 100 * @param buffer: address of the binary image (payload) 101 * @return: 0 on success, negative value in case of error 102 */ 103 int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer); 104 105 /* Functions to map DDR in MMU with non-cacheable attribute, and unmap it */ 106 int stm32mp_map_ddr_non_cacheable(void); 107 int stm32mp_unmap_ddr(void); 108 109 #endif /* STM32MP_COMMON_H */ 110