xref: /rk3399_ARM-atf/plat/st/common/include/stm32mp_common.h (revision ae3ce8b28eac73e9a41fdb28424d9f0f4b5f200e)
1c9d75b3cSYann Gautier /*
2*ae3ce8b2SLionel Debieve  * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved
3c9d75b3cSYann Gautier  *
4c9d75b3cSYann Gautier  * SPDX-License-Identifier: BSD-3-Clause
5c9d75b3cSYann Gautier  */
6c9d75b3cSYann Gautier 
7c9d75b3cSYann Gautier #ifndef STM32MP_COMMON_H
8c9d75b3cSYann Gautier #define STM32MP_COMMON_H
9c9d75b3cSYann Gautier 
103f9c9784SYann Gautier #include <stdbool.h>
113f9c9784SYann Gautier 
121e919529SYann Gautier #include <platform_def.h>
131e919529SYann Gautier 
143d201787SYann Gautier #define JEDEC_ST_BKID U(0x0)
153d201787SYann Gautier #define JEDEC_ST_MFID U(0x20)
163d201787SYann Gautier 
17c9d75b3cSYann Gautier /* Functions to save and get boot context address given by ROM code */
183f9c9784SYann Gautier void stm32mp_save_boot_ctx_address(uintptr_t address);
193f9c9784SYann Gautier uintptr_t stm32mp_get_boot_ctx_address(void);
207e87ba25SYann Gautier uint16_t stm32mp_get_boot_itf_selected(void);
21c9d75b3cSYann Gautier 
22b2182cdeSYann Gautier bool stm32mp_is_single_core(void);
23f700423cSLionel Debieve bool stm32mp_is_closed_device(void);
24b2182cdeSYann Gautier 
257ae58c6bSYann Gautier /* Return the base address of the DDR controller */
267ae58c6bSYann Gautier uintptr_t stm32mp_ddrctrl_base(void);
277ae58c6bSYann Gautier 
287ae58c6bSYann Gautier /* Return the base address of the DDR PHY */
297ae58c6bSYann Gautier uintptr_t stm32mp_ddrphyc_base(void);
307ae58c6bSYann Gautier 
317ae58c6bSYann Gautier /* Return the base address of the PWR peripheral */
327ae58c6bSYann Gautier uintptr_t stm32mp_pwr_base(void);
337ae58c6bSYann Gautier 
347ae58c6bSYann Gautier /* Return the base address of the RCC peripheral */
357ae58c6bSYann Gautier uintptr_t stm32mp_rcc_base(void);
367ae58c6bSYann Gautier 
37e463d3f4SYann Gautier /* Check MMU status to allow spinlock use */
38e463d3f4SYann Gautier bool stm32mp_lock_available(void);
39e463d3f4SYann Gautier 
40*ae3ce8b2SLionel Debieve int stm32_get_otp_index(const char *otp_name, uint32_t *otp_idx,
41*ae3ce8b2SLionel Debieve 			uint32_t *otp_len);
42*ae3ce8b2SLionel Debieve int stm32_get_otp_value(const char *otp_name, uint32_t *otp_val);
43*ae3ce8b2SLionel Debieve int stm32_get_otp_value_from_idx(const uint32_t otp_idx, uint32_t *otp_val);
44*ae3ce8b2SLionel Debieve 
4573680c23SYann Gautier /* Get IWDG platform instance ID from peripheral IO memory base address */
4673680c23SYann Gautier uint32_t stm32_iwdg_get_instance(uintptr_t base);
4773680c23SYann Gautier 
4873680c23SYann Gautier /* Return bitflag mask for expected IWDG configuration from OTP content */
4973680c23SYann Gautier uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst);
5073680c23SYann Gautier 
5173680c23SYann Gautier #if defined(IMAGE_BL2)
5273680c23SYann Gautier /* Update OTP shadow registers with IWDG configuration from device tree */
5373680c23SYann Gautier uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags);
5473680c23SYann Gautier #endif
5573680c23SYann Gautier 
56acf28c26SYann Gautier #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2)
579083fa11SPatrick Delaunay /* Get the UART address from its instance number */
589083fa11SPatrick Delaunay uintptr_t get_uart_address(uint32_t instance_nb);
599083fa11SPatrick Delaunay #endif
609083fa11SPatrick Delaunay 
6153612f72SYann Gautier /* Setup the UART console */
6253612f72SYann Gautier int stm32mp_uart_console_setup(void);
6353612f72SYann Gautier 
64c9d75b3cSYann Gautier /*
65c9d75b3cSYann Gautier  * Platform util functions for the GPIO driver
66c9d75b3cSYann Gautier  * @bank: Target GPIO bank ID as per DT bindings
67c9d75b3cSYann Gautier  *
68c9d75b3cSYann Gautier  * Platform shall implement these functions to provide to stm32_gpio
69c9d75b3cSYann Gautier  * driver the resource reference for a target GPIO bank. That are
70c9d75b3cSYann Gautier  * memory mapped interface base address, interface offset (see below)
71c9d75b3cSYann Gautier  * and clock identifier.
72c9d75b3cSYann Gautier  *
73c9d75b3cSYann Gautier  * stm32_get_gpio_bank_offset() returns a bank offset that is used to
74c9d75b3cSYann Gautier  * check DT configuration matches platform implementation of the banks
75c9d75b3cSYann Gautier  * description.
76c9d75b3cSYann Gautier  */
77c9d75b3cSYann Gautier uintptr_t stm32_get_gpio_bank_base(unsigned int bank);
78c9d75b3cSYann Gautier unsigned long stm32_get_gpio_bank_clock(unsigned int bank);
79c9d75b3cSYann Gautier uint32_t stm32_get_gpio_bank_offset(unsigned int bank);
80737ad29bSYann Gautier bool stm32_gpio_is_secure_at_reset(unsigned int bank);
81c9d75b3cSYann Gautier 
82ccc199edSEtienne Carriere /* Return node offset for target GPIO bank ID @bank or a FDT error code */
83ccc199edSEtienne Carriere int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank);
84ccc199edSEtienne Carriere 
8592661e01SYann Gautier /* Get the chip revision */
8692661e01SYann Gautier uint32_t stm32mp_get_chip_version(void);
8792661e01SYann Gautier /* Get the chip device ID */
8892661e01SYann Gautier uint32_t stm32mp_get_chip_dev_id(void);
8992661e01SYann Gautier 
9092661e01SYann Gautier /* Get SOC name */
9192661e01SYann Gautier #define STM32_SOC_NAME_SIZE 20
9292661e01SYann Gautier void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]);
9392661e01SYann Gautier 
94dec286ddSYann Gautier /* Print CPU information */
95dec286ddSYann Gautier void stm32mp_print_cpuinfo(void);
96dec286ddSYann Gautier 
9710e7a9e9SYann Gautier /* Print board information */
9810e7a9e9SYann Gautier void stm32mp_print_boardinfo(void);
9910e7a9e9SYann Gautier 
100c9d75b3cSYann Gautier /* Initialise the IO layer and register platform IO devices */
1013f9c9784SYann Gautier void stm32mp_io_setup(void);
102c9d75b3cSYann Gautier 
1031d204ee4SYann Gautier #if STM32MP_USE_STM32IMAGE
1041e919529SYann Gautier /*
1051e919529SYann Gautier  * Check that the STM32 header of a .stm32 binary image is valid
1061e919529SYann Gautier  * @param header: pointer to the stm32 image header
1071e919529SYann Gautier  * @param buffer: address of the binary image (payload)
1081e919529SYann Gautier  * @return: 0 on success, negative value in case of error
1091e919529SYann Gautier  */
1101e919529SYann Gautier int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer);
1111d204ee4SYann Gautier #endif /* STM32MP_USE_STM32IMAGE */
1121e919529SYann Gautier 
11384686ba3SYann Gautier /* Functions to map DDR in MMU with non-cacheable attribute, and unmap it */
11484686ba3SYann Gautier int stm32mp_map_ddr_non_cacheable(void);
11584686ba3SYann Gautier int stm32mp_unmap_ddr(void);
11684686ba3SYann Gautier 
117a6bfa75cSYann Gautier /* Functions to save and get boot peripheral info */
1184dc77a35SYann Gautier void stm32_save_boot_interface(uint32_t interface, uint32_t instance);
119a6bfa75cSYann Gautier void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance);
1204dc77a35SYann Gautier 
121ba02add9SSughosh Ganu #if !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT
122ba02add9SSughosh Ganu void stm32mp1_fwu_set_boot_idx(void);
123ba02add9SSughosh Ganu #endif /* !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT */
124ba02add9SSughosh Ganu 
125c9d75b3cSYann Gautier #endif /* STM32MP_COMMON_H */
126