1c9d75b3cSYann Gautier /* 2c9d75b3cSYann Gautier * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved 36f4572bdSYann Gautier * Copyright (c) 2018-2019, Linaro Limited 4c9d75b3cSYann Gautier * 5c9d75b3cSYann Gautier * SPDX-License-Identifier: BSD-3-Clause 6c9d75b3cSYann Gautier */ 7c9d75b3cSYann Gautier 8c9d75b3cSYann Gautier #ifndef STM32MP_COMMON_H 9c9d75b3cSYann Gautier #define STM32MP_COMMON_H 10c9d75b3cSYann Gautier 113f9c9784SYann Gautier #include <stdbool.h> 123f9c9784SYann Gautier 136f4572bdSYann Gautier #include <arch_helpers.h> 146f4572bdSYann Gautier 15c9d75b3cSYann Gautier /* Functions to save and get boot context address given by ROM code */ 163f9c9784SYann Gautier void stm32mp_save_boot_ctx_address(uintptr_t address); 173f9c9784SYann Gautier uintptr_t stm32mp_get_boot_ctx_address(void); 18c9d75b3cSYann Gautier 19*7ae58c6bSYann Gautier /* Return the base address of the DDR controller */ 20*7ae58c6bSYann Gautier uintptr_t stm32mp_ddrctrl_base(void); 21*7ae58c6bSYann Gautier 22*7ae58c6bSYann Gautier /* Return the base address of the DDR PHY */ 23*7ae58c6bSYann Gautier uintptr_t stm32mp_ddrphyc_base(void); 24*7ae58c6bSYann Gautier 25*7ae58c6bSYann Gautier /* Return the base address of the PWR peripheral */ 26*7ae58c6bSYann Gautier uintptr_t stm32mp_pwr_base(void); 27*7ae58c6bSYann Gautier 28*7ae58c6bSYann Gautier /* Return the base address of the RCC peripheral */ 29*7ae58c6bSYann Gautier uintptr_t stm32mp_rcc_base(void); 30*7ae58c6bSYann Gautier 31c9d75b3cSYann Gautier /* 32c9d75b3cSYann Gautier * Platform util functions for the GPIO driver 33c9d75b3cSYann Gautier * @bank: Target GPIO bank ID as per DT bindings 34c9d75b3cSYann Gautier * 35c9d75b3cSYann Gautier * Platform shall implement these functions to provide to stm32_gpio 36c9d75b3cSYann Gautier * driver the resource reference for a target GPIO bank. That are 37c9d75b3cSYann Gautier * memory mapped interface base address, interface offset (see below) 38c9d75b3cSYann Gautier * and clock identifier. 39c9d75b3cSYann Gautier * 40c9d75b3cSYann Gautier * stm32_get_gpio_bank_offset() returns a bank offset that is used to 41c9d75b3cSYann Gautier * check DT configuration matches platform implementation of the banks 42c9d75b3cSYann Gautier * description. 43c9d75b3cSYann Gautier */ 44c9d75b3cSYann Gautier uintptr_t stm32_get_gpio_bank_base(unsigned int bank); 45c9d75b3cSYann Gautier unsigned long stm32_get_gpio_bank_clock(unsigned int bank); 46c9d75b3cSYann Gautier uint32_t stm32_get_gpio_bank_offset(unsigned int bank); 47c9d75b3cSYann Gautier 483f9c9784SYann Gautier /* 493f9c9784SYann Gautier * Util for clock gating and to get clock rate for stm32 and platform drivers 503f9c9784SYann Gautier * @id: Target clock ID, ID used in clock DT bindings 513f9c9784SYann Gautier */ 523f9c9784SYann Gautier bool stm32mp_clk_is_enabled(unsigned long id); 533f9c9784SYann Gautier int stm32mp_clk_enable(unsigned long id); 543f9c9784SYann Gautier int stm32mp_clk_disable(unsigned long id); 553f9c9784SYann Gautier unsigned long stm32mp_clk_get_rate(unsigned long id); 563f9c9784SYann Gautier 57c9d75b3cSYann Gautier /* Initialise the IO layer and register platform IO devices */ 583f9c9784SYann Gautier void stm32mp_io_setup(void); 59c9d75b3cSYann Gautier 606f4572bdSYann Gautier static inline uint64_t arm_cnt_us2cnt(uint32_t us) 616f4572bdSYann Gautier { 626f4572bdSYann Gautier return ((uint64_t)us * (uint64_t)read_cntfrq()) / 1000000ULL; 636f4572bdSYann Gautier } 646f4572bdSYann Gautier 656f4572bdSYann Gautier static inline uint64_t timeout_init_us(uint32_t us) 666f4572bdSYann Gautier { 676f4572bdSYann Gautier return read_cntpct_el0() + arm_cnt_us2cnt(us); 686f4572bdSYann Gautier } 696f4572bdSYann Gautier 706f4572bdSYann Gautier static inline bool timeout_elapsed(uint64_t expire) 716f4572bdSYann Gautier { 726f4572bdSYann Gautier return read_cntpct_el0() > expire; 736f4572bdSYann Gautier } 746f4572bdSYann Gautier 75c9d75b3cSYann Gautier #endif /* STM32MP_COMMON_H */ 76