1c9d75b3cSYann Gautier /* 2c9d75b3cSYann Gautier * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved 36f4572bdSYann Gautier * Copyright (c) 2018-2019, Linaro Limited 4c9d75b3cSYann Gautier * 5c9d75b3cSYann Gautier * SPDX-License-Identifier: BSD-3-Clause 6c9d75b3cSYann Gautier */ 7c9d75b3cSYann Gautier 8c9d75b3cSYann Gautier #ifndef STM32MP_COMMON_H 9c9d75b3cSYann Gautier #define STM32MP_COMMON_H 10c9d75b3cSYann Gautier 113f9c9784SYann Gautier #include <stdbool.h> 123f9c9784SYann Gautier 136f4572bdSYann Gautier #include <arch_helpers.h> 146f4572bdSYann Gautier 15c9d75b3cSYann Gautier /* Functions to save and get boot context address given by ROM code */ 163f9c9784SYann Gautier void stm32mp_save_boot_ctx_address(uintptr_t address); 173f9c9784SYann Gautier uintptr_t stm32mp_get_boot_ctx_address(void); 18c9d75b3cSYann Gautier 197ae58c6bSYann Gautier /* Return the base address of the DDR controller */ 207ae58c6bSYann Gautier uintptr_t stm32mp_ddrctrl_base(void); 217ae58c6bSYann Gautier 227ae58c6bSYann Gautier /* Return the base address of the DDR PHY */ 237ae58c6bSYann Gautier uintptr_t stm32mp_ddrphyc_base(void); 247ae58c6bSYann Gautier 257ae58c6bSYann Gautier /* Return the base address of the PWR peripheral */ 267ae58c6bSYann Gautier uintptr_t stm32mp_pwr_base(void); 277ae58c6bSYann Gautier 287ae58c6bSYann Gautier /* Return the base address of the RCC peripheral */ 297ae58c6bSYann Gautier uintptr_t stm32mp_rcc_base(void); 307ae58c6bSYann Gautier 31*73680c23SYann Gautier /* Get IWDG platform instance ID from peripheral IO memory base address */ 32*73680c23SYann Gautier uint32_t stm32_iwdg_get_instance(uintptr_t base); 33*73680c23SYann Gautier 34*73680c23SYann Gautier /* Return bitflag mask for expected IWDG configuration from OTP content */ 35*73680c23SYann Gautier uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst); 36*73680c23SYann Gautier 37*73680c23SYann Gautier #if defined(IMAGE_BL2) 38*73680c23SYann Gautier /* Update OTP shadow registers with IWDG configuration from device tree */ 39*73680c23SYann Gautier uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags); 40*73680c23SYann Gautier #endif 41*73680c23SYann Gautier 42c9d75b3cSYann Gautier /* 43c9d75b3cSYann Gautier * Platform util functions for the GPIO driver 44c9d75b3cSYann Gautier * @bank: Target GPIO bank ID as per DT bindings 45c9d75b3cSYann Gautier * 46c9d75b3cSYann Gautier * Platform shall implement these functions to provide to stm32_gpio 47c9d75b3cSYann Gautier * driver the resource reference for a target GPIO bank. That are 48c9d75b3cSYann Gautier * memory mapped interface base address, interface offset (see below) 49c9d75b3cSYann Gautier * and clock identifier. 50c9d75b3cSYann Gautier * 51c9d75b3cSYann Gautier * stm32_get_gpio_bank_offset() returns a bank offset that is used to 52c9d75b3cSYann Gautier * check DT configuration matches platform implementation of the banks 53c9d75b3cSYann Gautier * description. 54c9d75b3cSYann Gautier */ 55c9d75b3cSYann Gautier uintptr_t stm32_get_gpio_bank_base(unsigned int bank); 56c9d75b3cSYann Gautier unsigned long stm32_get_gpio_bank_clock(unsigned int bank); 57c9d75b3cSYann Gautier uint32_t stm32_get_gpio_bank_offset(unsigned int bank); 58c9d75b3cSYann Gautier 593f9c9784SYann Gautier /* 603f9c9784SYann Gautier * Util for clock gating and to get clock rate for stm32 and platform drivers 613f9c9784SYann Gautier * @id: Target clock ID, ID used in clock DT bindings 623f9c9784SYann Gautier */ 633f9c9784SYann Gautier bool stm32mp_clk_is_enabled(unsigned long id); 640d21680cSYann Gautier void stm32mp_clk_enable(unsigned long id); 650d21680cSYann Gautier void stm32mp_clk_disable(unsigned long id); 663f9c9784SYann Gautier unsigned long stm32mp_clk_get_rate(unsigned long id); 673f9c9784SYann Gautier 68c9d75b3cSYann Gautier /* Initialise the IO layer and register platform IO devices */ 693f9c9784SYann Gautier void stm32mp_io_setup(void); 70c9d75b3cSYann Gautier 716f4572bdSYann Gautier static inline uint64_t arm_cnt_us2cnt(uint32_t us) 726f4572bdSYann Gautier { 736f4572bdSYann Gautier return ((uint64_t)us * (uint64_t)read_cntfrq()) / 1000000ULL; 746f4572bdSYann Gautier } 756f4572bdSYann Gautier 766f4572bdSYann Gautier static inline uint64_t timeout_init_us(uint32_t us) 776f4572bdSYann Gautier { 786f4572bdSYann Gautier return read_cntpct_el0() + arm_cnt_us2cnt(us); 796f4572bdSYann Gautier } 806f4572bdSYann Gautier 816f4572bdSYann Gautier static inline bool timeout_elapsed(uint64_t expire) 826f4572bdSYann Gautier { 836f4572bdSYann Gautier return read_cntpct_el0() > expire; 846f4572bdSYann Gautier } 856f4572bdSYann Gautier 86c9d75b3cSYann Gautier #endif /* STM32MP_COMMON_H */ 87