1c9d75b3cSYann Gautier /* 2c9d75b3cSYann Gautier * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved 3*6f4572bdSYann Gautier * Copyright (c) 2018-2019, Linaro Limited 4c9d75b3cSYann Gautier * 5c9d75b3cSYann Gautier * SPDX-License-Identifier: BSD-3-Clause 6c9d75b3cSYann Gautier */ 7c9d75b3cSYann Gautier 8c9d75b3cSYann Gautier #ifndef STM32MP_COMMON_H 9c9d75b3cSYann Gautier #define STM32MP_COMMON_H 10c9d75b3cSYann Gautier 113f9c9784SYann Gautier #include <stdbool.h> 123f9c9784SYann Gautier 13*6f4572bdSYann Gautier #include <arch_helpers.h> 14*6f4572bdSYann Gautier 15c9d75b3cSYann Gautier /* Functions to save and get boot context address given by ROM code */ 163f9c9784SYann Gautier void stm32mp_save_boot_ctx_address(uintptr_t address); 173f9c9784SYann Gautier uintptr_t stm32mp_get_boot_ctx_address(void); 18c9d75b3cSYann Gautier 19c9d75b3cSYann Gautier /* 20c9d75b3cSYann Gautier * Platform util functions for the GPIO driver 21c9d75b3cSYann Gautier * @bank: Target GPIO bank ID as per DT bindings 22c9d75b3cSYann Gautier * 23c9d75b3cSYann Gautier * Platform shall implement these functions to provide to stm32_gpio 24c9d75b3cSYann Gautier * driver the resource reference for a target GPIO bank. That are 25c9d75b3cSYann Gautier * memory mapped interface base address, interface offset (see below) 26c9d75b3cSYann Gautier * and clock identifier. 27c9d75b3cSYann Gautier * 28c9d75b3cSYann Gautier * stm32_get_gpio_bank_offset() returns a bank offset that is used to 29c9d75b3cSYann Gautier * check DT configuration matches platform implementation of the banks 30c9d75b3cSYann Gautier * description. 31c9d75b3cSYann Gautier */ 32c9d75b3cSYann Gautier uintptr_t stm32_get_gpio_bank_base(unsigned int bank); 33c9d75b3cSYann Gautier unsigned long stm32_get_gpio_bank_clock(unsigned int bank); 34c9d75b3cSYann Gautier uint32_t stm32_get_gpio_bank_offset(unsigned int bank); 35c9d75b3cSYann Gautier 363f9c9784SYann Gautier /* 373f9c9784SYann Gautier * Util for clock gating and to get clock rate for stm32 and platform drivers 383f9c9784SYann Gautier * @id: Target clock ID, ID used in clock DT bindings 393f9c9784SYann Gautier */ 403f9c9784SYann Gautier bool stm32mp_clk_is_enabled(unsigned long id); 413f9c9784SYann Gautier int stm32mp_clk_enable(unsigned long id); 423f9c9784SYann Gautier int stm32mp_clk_disable(unsigned long id); 433f9c9784SYann Gautier unsigned long stm32mp_clk_get_rate(unsigned long id); 443f9c9784SYann Gautier 45c9d75b3cSYann Gautier /* Initialise the IO layer and register platform IO devices */ 463f9c9784SYann Gautier void stm32mp_io_setup(void); 47c9d75b3cSYann Gautier 48*6f4572bdSYann Gautier static inline uint64_t arm_cnt_us2cnt(uint32_t us) 49*6f4572bdSYann Gautier { 50*6f4572bdSYann Gautier return ((uint64_t)us * (uint64_t)read_cntfrq()) / 1000000ULL; 51*6f4572bdSYann Gautier } 52*6f4572bdSYann Gautier 53*6f4572bdSYann Gautier static inline uint64_t timeout_init_us(uint32_t us) 54*6f4572bdSYann Gautier { 55*6f4572bdSYann Gautier return read_cntpct_el0() + arm_cnt_us2cnt(us); 56*6f4572bdSYann Gautier } 57*6f4572bdSYann Gautier 58*6f4572bdSYann Gautier static inline bool timeout_elapsed(uint64_t expire) 59*6f4572bdSYann Gautier { 60*6f4572bdSYann Gautier return read_cntpct_el0() > expire; 61*6f4572bdSYann Gautier } 62*6f4572bdSYann Gautier 63c9d75b3cSYann Gautier #endif /* STM32MP_COMMON_H */ 64