1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <drivers/io/io_block.h> 15 #include <drivers/io/io_driver.h> 16 #include <drivers/io/io_dummy.h> 17 #include <drivers/io/io_mtd.h> 18 #include <drivers/io/io_storage.h> 19 #include <drivers/mmc.h> 20 #include <drivers/partition/partition.h> 21 #include <drivers/raw_nand.h> 22 #include <drivers/spi_nand.h> 23 #include <drivers/spi_nor.h> 24 #include <drivers/st/io_mmc.h> 25 #include <drivers/st/io_stm32image.h> 26 #include <drivers/st/stm32_fmc2_nand.h> 27 #include <drivers/st/stm32_qspi.h> 28 #include <drivers/st/stm32_sdmmc2.h> 29 #include <lib/mmio.h> 30 #include <lib/utils.h> 31 #include <plat/common/platform.h> 32 33 /* IO devices */ 34 static const io_dev_connector_t *dummy_dev_con; 35 static uintptr_t dummy_dev_handle; 36 static uintptr_t dummy_dev_spec; 37 38 static uintptr_t image_dev_handle; 39 static uintptr_t storage_dev_handle; 40 41 #if STM32MP_SDMMC || STM32MP_EMMC 42 static io_block_spec_t gpt_block_spec = { 43 .offset = 0, 44 .length = 34 * MMC_BLOCK_SIZE, /* Size of GPT table */ 45 }; 46 47 static uint32_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE); 48 49 static const io_block_dev_spec_t mmc_block_dev_spec = { 50 /* It's used as temp buffer in block driver */ 51 .buffer = { 52 .offset = (size_t)&block_buffer, 53 .length = MMC_BLOCK_SIZE, 54 }, 55 .ops = { 56 .read = mmc_read_blocks, 57 .write = NULL, 58 }, 59 .block_size = MMC_BLOCK_SIZE, 60 }; 61 62 static const io_dev_connector_t *mmc_dev_con; 63 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 64 65 #if STM32MP_SPI_NOR 66 static io_mtd_dev_spec_t spi_nor_dev_spec = { 67 .ops = { 68 .init = spi_nor_init, 69 .read = spi_nor_read, 70 }, 71 }; 72 #endif 73 74 #if STM32MP_RAW_NAND 75 static io_mtd_dev_spec_t nand_dev_spec = { 76 .ops = { 77 .init = nand_raw_init, 78 .read = nand_read, 79 }, 80 }; 81 82 static const io_dev_connector_t *nand_dev_con; 83 #endif 84 85 #if STM32MP_SPI_NAND 86 static io_mtd_dev_spec_t spi_nand_dev_spec = { 87 .ops = { 88 .init = spi_nand_init, 89 .read = nand_read, 90 }, 91 }; 92 #endif 93 94 #if STM32MP_SPI_NAND || STM32MP_SPI_NOR 95 static const io_dev_connector_t *spi_dev_con; 96 #endif 97 98 #ifdef AARCH32_SP_OPTEE 99 static const struct stm32image_part_info optee_header_partition_spec = { 100 .name = OPTEE_HEADER_IMAGE_NAME, 101 .binary_type = OPTEE_HEADER_BINARY_TYPE, 102 }; 103 104 static const struct stm32image_part_info optee_pager_partition_spec = { 105 .name = OPTEE_PAGER_IMAGE_NAME, 106 .binary_type = OPTEE_PAGER_BINARY_TYPE, 107 }; 108 109 static const struct stm32image_part_info optee_paged_partition_spec = { 110 .name = OPTEE_PAGED_IMAGE_NAME, 111 .binary_type = OPTEE_PAGED_BINARY_TYPE, 112 }; 113 #else 114 static const io_block_spec_t bl32_block_spec = { 115 .offset = BL32_BASE, 116 .length = STM32MP_BL32_SIZE 117 }; 118 #endif 119 120 static const io_block_spec_t bl2_block_spec = { 121 .offset = BL2_BASE, 122 .length = STM32MP_BL2_SIZE, 123 }; 124 125 static const struct stm32image_part_info bl33_partition_spec = { 126 .name = BL33_IMAGE_NAME, 127 .binary_type = BL33_BINARY_TYPE, 128 }; 129 130 enum { 131 IMG_IDX_BL33, 132 #ifdef AARCH32_SP_OPTEE 133 IMG_IDX_OPTEE_HEADER, 134 IMG_IDX_OPTEE_PAGER, 135 IMG_IDX_OPTEE_PAGED, 136 #endif 137 IMG_IDX_NUM 138 }; 139 140 static struct stm32image_device_info stm32image_dev_info_spec __unused = { 141 .lba_size = MMC_BLOCK_SIZE, 142 .part_info[IMG_IDX_BL33] = { 143 .name = BL33_IMAGE_NAME, 144 .binary_type = BL33_BINARY_TYPE, 145 }, 146 #ifdef AARCH32_SP_OPTEE 147 .part_info[IMG_IDX_OPTEE_HEADER] = { 148 .name = OPTEE_HEADER_IMAGE_NAME, 149 .binary_type = OPTEE_HEADER_BINARY_TYPE, 150 }, 151 .part_info[IMG_IDX_OPTEE_PAGER] = { 152 .name = OPTEE_PAGER_IMAGE_NAME, 153 .binary_type = OPTEE_PAGER_BINARY_TYPE, 154 }, 155 .part_info[IMG_IDX_OPTEE_PAGED] = { 156 .name = OPTEE_PAGED_IMAGE_NAME, 157 .binary_type = OPTEE_PAGED_BINARY_TYPE, 158 }, 159 #endif 160 }; 161 162 static io_block_spec_t stm32image_block_spec = { 163 .offset = 0, 164 .length = 0, 165 }; 166 167 static const io_dev_connector_t *stm32image_dev_con __unused; 168 169 static int open_dummy(const uintptr_t spec); 170 static int open_image(const uintptr_t spec); 171 static int open_storage(const uintptr_t spec); 172 173 struct plat_io_policy { 174 uintptr_t *dev_handle; 175 uintptr_t image_spec; 176 int (*check)(const uintptr_t spec); 177 }; 178 179 static const struct plat_io_policy policies[] = { 180 [BL2_IMAGE_ID] = { 181 .dev_handle = &dummy_dev_handle, 182 .image_spec = (uintptr_t)&bl2_block_spec, 183 .check = open_dummy 184 }, 185 #ifdef AARCH32_SP_OPTEE 186 [BL32_IMAGE_ID] = { 187 .dev_handle = &image_dev_handle, 188 .image_spec = (uintptr_t)&optee_header_partition_spec, 189 .check = open_image 190 }, 191 [BL32_EXTRA1_IMAGE_ID] = { 192 .dev_handle = &image_dev_handle, 193 .image_spec = (uintptr_t)&optee_pager_partition_spec, 194 .check = open_image 195 }, 196 [BL32_EXTRA2_IMAGE_ID] = { 197 .dev_handle = &image_dev_handle, 198 .image_spec = (uintptr_t)&optee_paged_partition_spec, 199 .check = open_image 200 }, 201 #else 202 [BL32_IMAGE_ID] = { 203 .dev_handle = &dummy_dev_handle, 204 .image_spec = (uintptr_t)&bl32_block_spec, 205 .check = open_dummy 206 }, 207 #endif 208 [BL33_IMAGE_ID] = { 209 .dev_handle = &image_dev_handle, 210 .image_spec = (uintptr_t)&bl33_partition_spec, 211 .check = open_image 212 }, 213 #if STM32MP_SDMMC || STM32MP_EMMC 214 [GPT_IMAGE_ID] = { 215 .dev_handle = &storage_dev_handle, 216 .image_spec = (uintptr_t)&gpt_block_spec, 217 .check = open_storage 218 }, 219 #endif 220 [STM32_IMAGE_ID] = { 221 .dev_handle = &storage_dev_handle, 222 .image_spec = (uintptr_t)&stm32image_block_spec, 223 .check = open_storage 224 } 225 }; 226 227 static int open_dummy(const uintptr_t spec) 228 { 229 return io_dev_init(dummy_dev_handle, 0); 230 } 231 232 static int open_image(const uintptr_t spec) 233 { 234 return io_dev_init(image_dev_handle, 0); 235 } 236 237 static int open_storage(const uintptr_t spec) 238 { 239 return io_dev_init(storage_dev_handle, 0); 240 } 241 242 static void print_boot_device(boot_api_context_t *boot_context) 243 { 244 switch (boot_context->boot_interface_selected) { 245 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 246 INFO("Using SDMMC\n"); 247 break; 248 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 249 INFO("Using EMMC\n"); 250 break; 251 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 252 INFO("Using QSPI NOR\n"); 253 break; 254 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 255 INFO("Using FMC NAND\n"); 256 break; 257 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 258 INFO("Using SPI NAND\n"); 259 break; 260 default: 261 ERROR("Boot interface not found\n"); 262 panic(); 263 break; 264 } 265 266 if (boot_context->boot_interface_instance != 0U) { 267 INFO(" Instance %d\n", boot_context->boot_interface_instance); 268 } 269 } 270 271 #if STM32MP_SDMMC || STM32MP_EMMC 272 static void boot_mmc(enum mmc_device_type mmc_dev_type, 273 uint16_t boot_interface_instance) 274 { 275 int io_result __unused; 276 uint8_t idx; 277 struct stm32image_part_info *part; 278 struct stm32_sdmmc2_params params; 279 struct mmc_device_info device_info; 280 const partition_entry_t *entry; 281 282 zeromem(&device_info, sizeof(struct mmc_device_info)); 283 zeromem(¶ms, sizeof(struct stm32_sdmmc2_params)); 284 285 device_info.mmc_dev_type = mmc_dev_type; 286 287 switch (boot_interface_instance) { 288 case 1: 289 params.reg_base = STM32MP_SDMMC1_BASE; 290 break; 291 case 2: 292 params.reg_base = STM32MP_SDMMC2_BASE; 293 break; 294 case 3: 295 params.reg_base = STM32MP_SDMMC3_BASE; 296 break; 297 default: 298 WARN("SDMMC instance not found, using default\n"); 299 if (mmc_dev_type == MMC_IS_SD) { 300 params.reg_base = STM32MP_SDMMC1_BASE; 301 } else { 302 params.reg_base = STM32MP_SDMMC2_BASE; 303 } 304 break; 305 } 306 307 params.device_info = &device_info; 308 if (stm32_sdmmc2_mmc_init(¶ms) != 0) { 309 ERROR("SDMMC%u init failed\n", boot_interface_instance); 310 panic(); 311 } 312 313 /* Open MMC as a block device to read GPT table */ 314 io_result = register_io_dev_block(&mmc_dev_con); 315 if (io_result != 0) { 316 panic(); 317 } 318 319 io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec, 320 &storage_dev_handle); 321 assert(io_result == 0); 322 323 partition_init(GPT_IMAGE_ID); 324 325 io_result = io_dev_close(storage_dev_handle); 326 assert(io_result == 0); 327 328 stm32image_dev_info_spec.device_size = 329 stm32_sdmmc2_mmc_get_device_size(); 330 331 for (idx = 0U; idx < IMG_IDX_NUM; idx++) { 332 part = &stm32image_dev_info_spec.part_info[idx]; 333 entry = get_partition_entry(part->name); 334 if (entry == NULL) { 335 ERROR("Partition %s not found\n", part->name); 336 panic(); 337 } 338 339 part->part_offset = entry->start; 340 part->bkp_offset = 0U; 341 } 342 343 /* 344 * Re-open MMC with io_mmc, for better perfs compared to 345 * io_block. 346 */ 347 io_result = register_io_dev_mmc(&mmc_dev_con); 348 assert(io_result == 0); 349 350 io_result = io_dev_open(mmc_dev_con, 0, &storage_dev_handle); 351 assert(io_result == 0); 352 353 io_result = register_io_dev_stm32image(&stm32image_dev_con); 354 assert(io_result == 0); 355 356 io_result = io_dev_open(stm32image_dev_con, 357 (uintptr_t)&stm32image_dev_info_spec, 358 &image_dev_handle); 359 assert(io_result == 0); 360 } 361 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 362 363 #if STM32MP_SPI_NOR 364 static void boot_spi_nor(boot_api_context_t *boot_context) 365 { 366 int io_result __unused; 367 uint8_t idx; 368 struct stm32image_part_info *part; 369 370 io_result = stm32_qspi_init(); 371 assert(io_result == 0); 372 373 io_result = register_io_dev_mtd(&spi_dev_con); 374 assert(io_result == 0); 375 376 /* Open connections to device */ 377 io_result = io_dev_open(spi_dev_con, 378 (uintptr_t)&spi_nor_dev_spec, 379 &storage_dev_handle); 380 assert(io_result == 0); 381 382 stm32image_dev_info_spec.device_size = spi_nor_dev_spec.device_size; 383 384 idx = IMG_IDX_BL33; 385 part = &stm32image_dev_info_spec.part_info[idx]; 386 part->part_offset = STM32MP_NOR_BL33_OFFSET; 387 part->bkp_offset = 0U; 388 389 #ifdef AARCH32_SP_OPTEE 390 idx = IMG_IDX_OPTEE_HEADER; 391 part = &stm32image_dev_info_spec.part_info[idx]; 392 part->part_offset = STM32MP_NOR_TEEH_OFFSET; 393 part->bkp_offset = 0U; 394 395 idx = IMG_IDX_OPTEE_PAGED; 396 part = &stm32image_dev_info_spec.part_info[idx]; 397 part->part_offset = STM32MP_NOR_TEED_OFFSET; 398 part->bkp_offset = 0U; 399 400 idx = IMG_IDX_OPTEE_PAGER; 401 part = &stm32image_dev_info_spec.part_info[idx]; 402 part->part_offset = STM32MP_NOR_TEEX_OFFSET; 403 part->bkp_offset = 0U; 404 #endif 405 406 io_result = register_io_dev_stm32image(&stm32image_dev_con); 407 assert(io_result == 0); 408 409 io_result = io_dev_open(stm32image_dev_con, 410 (uintptr_t)&stm32image_dev_info_spec, 411 &image_dev_handle); 412 assert(io_result == 0); 413 } 414 #endif /* STM32MP_SPI_NOR */ 415 416 #if STM32MP_RAW_NAND 417 static void boot_fmc2_nand(boot_api_context_t *boot_context) 418 { 419 int io_result __unused; 420 uint8_t idx; 421 struct stm32image_part_info *part; 422 423 io_result = stm32_fmc2_init(); 424 assert(io_result == 0); 425 426 /* Register the IO device on this platform */ 427 io_result = register_io_dev_mtd(&nand_dev_con); 428 assert(io_result == 0); 429 430 /* Open connections to device */ 431 io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec, 432 &storage_dev_handle); 433 assert(io_result == 0); 434 435 stm32image_dev_info_spec.device_size = nand_dev_spec.device_size; 436 437 idx = IMG_IDX_BL33; 438 part = &stm32image_dev_info_spec.part_info[idx]; 439 part->part_offset = STM32MP_NAND_BL33_OFFSET; 440 part->bkp_offset = nand_dev_spec.erase_size; 441 442 #ifdef AARCH32_SP_OPTEE 443 idx = IMG_IDX_OPTEE_HEADER; 444 part = &stm32image_dev_info_spec.part_info[idx]; 445 part->part_offset = STM32MP_NAND_TEEH_OFFSET; 446 part->bkp_offset = nand_dev_spec.erase_size; 447 448 idx = IMG_IDX_OPTEE_PAGED; 449 part = &stm32image_dev_info_spec.part_info[idx]; 450 part->part_offset = STM32MP_NAND_TEED_OFFSET; 451 part->bkp_offset = nand_dev_spec.erase_size; 452 453 idx = IMG_IDX_OPTEE_PAGER; 454 part = &stm32image_dev_info_spec.part_info[idx]; 455 part->part_offset = STM32MP_NAND_TEEX_OFFSET; 456 part->bkp_offset = nand_dev_spec.erase_size; 457 #endif 458 459 io_result = register_io_dev_stm32image(&stm32image_dev_con); 460 assert(io_result == 0); 461 462 io_result = io_dev_open(stm32image_dev_con, 463 (uintptr_t)&stm32image_dev_info_spec, 464 &image_dev_handle); 465 assert(io_result == 0); 466 } 467 #endif /* STM32MP_RAW_NAND */ 468 469 #if STM32MP_SPI_NAND 470 static void boot_spi_nand(boot_api_context_t *boot_context) 471 { 472 int io_result __unused; 473 uint8_t idx; 474 struct stm32image_part_info *part; 475 476 io_result = stm32_qspi_init(); 477 assert(io_result == 0); 478 479 io_result = register_io_dev_mtd(&spi_dev_con); 480 assert(io_result == 0); 481 482 /* Open connections to device */ 483 io_result = io_dev_open(spi_dev_con, 484 (uintptr_t)&spi_nand_dev_spec, 485 &storage_dev_handle); 486 assert(io_result == 0); 487 488 stm32image_dev_info_spec.device_size = 489 spi_nand_dev_spec.device_size; 490 491 idx = IMG_IDX_BL33; 492 part = &stm32image_dev_info_spec.part_info[idx]; 493 part->part_offset = STM32MP_NAND_BL33_OFFSET; 494 part->bkp_offset = spi_nand_dev_spec.erase_size; 495 496 #ifdef AARCH32_SP_OPTEE 497 idx = IMG_IDX_OPTEE_HEADER; 498 part = &stm32image_dev_info_spec.part_info[idx]; 499 part->part_offset = STM32MP_NAND_TEEH_OFFSET; 500 part->bkp_offset = spi_nand_dev_spec.erase_size; 501 502 idx = IMG_IDX_OPTEE_PAGED; 503 part = &stm32image_dev_info_spec.part_info[idx]; 504 part->part_offset = STM32MP_NAND_TEED_OFFSET; 505 part->bkp_offset = spi_nand_dev_spec.erase_size; 506 507 idx = IMG_IDX_OPTEE_PAGER; 508 part = &stm32image_dev_info_spec.part_info[idx]; 509 part->part_offset = STM32MP_NAND_TEEX_OFFSET; 510 part->bkp_offset = spi_nand_dev_spec.erase_size; 511 #endif 512 513 io_result = register_io_dev_stm32image(&stm32image_dev_con); 514 assert(io_result == 0); 515 516 io_result = io_dev_open(stm32image_dev_con, 517 (uintptr_t)&stm32image_dev_info_spec, 518 &image_dev_handle); 519 assert(io_result == 0); 520 } 521 #endif /* STM32MP_SPI_NAND */ 522 523 void stm32mp_io_setup(void) 524 { 525 int io_result __unused; 526 boot_api_context_t *boot_context = 527 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 528 529 print_boot_device(boot_context); 530 531 if ((boot_context->boot_partition_used_toboot == 1U) || 532 (boot_context->boot_partition_used_toboot == 2U)) { 533 INFO("Boot used partition fsbl%d\n", 534 boot_context->boot_partition_used_toboot); 535 } 536 537 io_result = register_io_dev_dummy(&dummy_dev_con); 538 assert(io_result == 0); 539 540 io_result = io_dev_open(dummy_dev_con, dummy_dev_spec, 541 &dummy_dev_handle); 542 assert(io_result == 0); 543 544 switch (boot_context->boot_interface_selected) { 545 #if STM32MP_SDMMC 546 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 547 dmbsy(); 548 boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance); 549 break; 550 #endif 551 #if STM32MP_EMMC 552 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 553 dmbsy(); 554 boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance); 555 break; 556 #endif 557 #if STM32MP_SPI_NOR 558 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI: 559 dmbsy(); 560 boot_spi_nor(boot_context); 561 break; 562 #endif 563 #if STM32MP_RAW_NAND 564 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 565 dmbsy(); 566 boot_fmc2_nand(boot_context); 567 break; 568 #endif 569 #if STM32MP_SPI_NAND 570 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI: 571 dmbsy(); 572 boot_spi_nand(boot_context); 573 break; 574 #endif 575 576 default: 577 ERROR("Boot interface %d not supported\n", 578 boot_context->boot_interface_selected); 579 break; 580 } 581 } 582 583 /* 584 * Return an IO device handle and specification which can be used to access 585 * an image. Use this to enforce platform load policy. 586 */ 587 int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, 588 uintptr_t *image_spec) 589 { 590 int rc; 591 const struct plat_io_policy *policy; 592 593 assert(image_id < ARRAY_SIZE(policies)); 594 595 policy = &policies[image_id]; 596 rc = policy->check(policy->image_spec); 597 if (rc == 0) { 598 *image_spec = policy->image_spec; 599 *dev_handle = *(policy->dev_handle); 600 } 601 602 return rc; 603 } 604