1*d8e919c7SMasahiro Yamada /* 2*d8e919c7SMasahiro Yamada * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*d8e919c7SMasahiro Yamada * 4*d8e919c7SMasahiro Yamada * SPDX-License-Identifier: BSD-3-Clause 5*d8e919c7SMasahiro Yamada */ 6*d8e919c7SMasahiro Yamada 7*d8e919c7SMasahiro Yamada #include <debug.h> 8*d8e919c7SMasahiro Yamada #include <platform_def.h> 9*d8e919c7SMasahiro Yamada #include <xlat_tables_v2.h> 10*d8e919c7SMasahiro Yamada 11*d8e919c7SMasahiro Yamada #define UNIPHIER_OCM_REGION_BASE 0x30000000 12*d8e919c7SMasahiro Yamada #define UNIPHIER_OCM_REGION_SIZE 0x00040000 13*d8e919c7SMasahiro Yamada 14*d8e919c7SMasahiro Yamada #define UNIPHIER_REG_REGION_BASE 0x50000000 15*d8e919c7SMasahiro Yamada #define UNIPHIER_REG_REGION_SIZE 0x20000000 16*d8e919c7SMasahiro Yamada 17*d8e919c7SMasahiro Yamada void uniphier_mmap_setup(uintptr_t total_base, size_t total_size, 18*d8e919c7SMasahiro Yamada const struct mmap_region *mmap) 19*d8e919c7SMasahiro Yamada { 20*d8e919c7SMasahiro Yamada VERBOSE("Trusted RAM seen by this BL image: %p - %p\n", 21*d8e919c7SMasahiro Yamada (void *)total_base, (void *)(total_base + total_size)); 22*d8e919c7SMasahiro Yamada mmap_add_region(total_base, total_base, 23*d8e919c7SMasahiro Yamada total_size, 24*d8e919c7SMasahiro Yamada MT_MEMORY | MT_RW | MT_SECURE); 25*d8e919c7SMasahiro Yamada 26*d8e919c7SMasahiro Yamada /* remap the code section */ 27*d8e919c7SMasahiro Yamada VERBOSE("Code region: %p - %p\n", 28*d8e919c7SMasahiro Yamada (void *)BL_CODE_BASE, (void *)BL_CODE_END); 29*d8e919c7SMasahiro Yamada mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 30*d8e919c7SMasahiro Yamada round_up(BL_CODE_END, PAGE_SIZE) - BL_CODE_BASE, 31*d8e919c7SMasahiro Yamada MT_CODE | MT_SECURE); 32*d8e919c7SMasahiro Yamada 33*d8e919c7SMasahiro Yamada /* remap the coherent memory region */ 34*d8e919c7SMasahiro Yamada VERBOSE("Coherent region: %p - %p\n", 35*d8e919c7SMasahiro Yamada (void *)BL_COHERENT_RAM_BASE, (void *)BL_COHERENT_RAM_END); 36*d8e919c7SMasahiro Yamada mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 37*d8e919c7SMasahiro Yamada BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 38*d8e919c7SMasahiro Yamada MT_DEVICE | MT_RW | MT_SECURE); 39*d8e919c7SMasahiro Yamada 40*d8e919c7SMasahiro Yamada /* 41*d8e919c7SMasahiro Yamada * on-chip SRAM region: should be DEVICE attribute because the USB 42*d8e919c7SMasahiro Yamada * load functions provided by the ROM use this memory region as a work 43*d8e919c7SMasahiro Yamada * area, but do not cater to cache coherency. 44*d8e919c7SMasahiro Yamada */ 45*d8e919c7SMasahiro Yamada mmap_add_region(UNIPHIER_OCM_REGION_BASE, UNIPHIER_OCM_REGION_BASE, 46*d8e919c7SMasahiro Yamada UNIPHIER_OCM_REGION_SIZE, 47*d8e919c7SMasahiro Yamada MT_DEVICE | MT_RW | MT_SECURE); 48*d8e919c7SMasahiro Yamada 49*d8e919c7SMasahiro Yamada /* register region */ 50*d8e919c7SMasahiro Yamada mmap_add_region(UNIPHIER_REG_REGION_BASE, UNIPHIER_REG_REGION_BASE, 51*d8e919c7SMasahiro Yamada UNIPHIER_REG_REGION_SIZE, 52*d8e919c7SMasahiro Yamada MT_DEVICE | MT_RW | MT_SECURE); 53*d8e919c7SMasahiro Yamada 54*d8e919c7SMasahiro Yamada /* additional regions if needed */ 55*d8e919c7SMasahiro Yamada if (mmap) 56*d8e919c7SMasahiro Yamada mmap_add(mmap); 57*d8e919c7SMasahiro Yamada 58*d8e919c7SMasahiro Yamada init_xlat_tables(); 59*d8e919c7SMasahiro Yamada } 60