1*d8e919c7SMasahiro Yamada/* 2*d8e919c7SMasahiro Yamada * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*d8e919c7SMasahiro Yamada * 4*d8e919c7SMasahiro Yamada * SPDX-License-Identifier: BSD-3-Clause 5*d8e919c7SMasahiro Yamada */ 6*d8e919c7SMasahiro Yamada 7*d8e919c7SMasahiro Yamada#include <asm_macros.S> 8*d8e919c7SMasahiro Yamada#include <platform_def.h> 9*d8e919c7SMasahiro Yamada 10*d8e919c7SMasahiro Yamada .global uniphier_calc_core_pos 11*d8e919c7SMasahiro Yamada .global plat_my_core_pos 12*d8e919c7SMasahiro Yamada .globl platform_mem_init 13*d8e919c7SMasahiro Yamada 14*d8e919c7SMasahiro Yamada/* 15*d8e919c7SMasahiro Yamada * unsigned int uniphier_calc_core_pos(u_register_t mpidr) 16*d8e919c7SMasahiro Yamada * core_pos = (cluster_id * max_cpus_per_cluster) + core_id 17*d8e919c7SMasahiro Yamada */ 18*d8e919c7SMasahiro Yamadafunc uniphier_calc_core_pos 19*d8e919c7SMasahiro Yamada and x1, x0, #MPIDR_CPU_MASK 20*d8e919c7SMasahiro Yamada and x0, x0, #MPIDR_CLUSTER_MASK 21*d8e919c7SMasahiro Yamada lsr x0, x0, #MPIDR_AFFINITY_BITS 22*d8e919c7SMasahiro Yamada mov x2, #UNIPHIER_MAX_CPUS_PER_CLUSTER 23*d8e919c7SMasahiro Yamada madd x0, x0, x2, x1 24*d8e919c7SMasahiro Yamada ret 25*d8e919c7SMasahiro Yamadaendfunc uniphier_calc_core_pos 26*d8e919c7SMasahiro Yamada 27*d8e919c7SMasahiro Yamadafunc plat_my_core_pos 28*d8e919c7SMasahiro Yamada mrs x0, mpidr_el1 29*d8e919c7SMasahiro Yamada b uniphier_calc_core_pos 30*d8e919c7SMasahiro Yamadaendfunc plat_my_core_pos 31*d8e919c7SMasahiro Yamada 32*d8e919c7SMasahiro Yamadafunc platform_mem_init 33*d8e919c7SMasahiro Yamada ret 34*d8e919c7SMasahiro Yamadaendfunc platform_mem_init 35