1 /* 2 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdint.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <drivers/io/io_block.h> 14 #include <lib/mmio.h> 15 #include <lib/utils_def.h> 16 17 #include "uniphier.h" 18 19 #define MMC_CMD_SWITCH 6 20 #define MMC_CMD_SELECT_CARD 7 21 #define MMC_CMD_SEND_CSD 9 22 #define MMC_CMD_READ_MULTIPLE_BLOCK 18 23 24 #define EXT_CSD_PART_CONF 179 /* R/W */ 25 26 #define MMC_RSP_PRESENT BIT(0) 27 #define MMC_RSP_136 BIT(1) /* 136 bit response */ 28 #define MMC_RSP_CRC BIT(2) /* expect valid crc */ 29 #define MMC_RSP_BUSY BIT(3) /* card may send busy */ 30 #define MMC_RSP_OPCODE BIT(4) /* response contains opcode */ 31 32 #define MMC_RSP_NONE (0) 33 #define MMC_RSP_R1 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE) 34 #define MMC_RSP_R1b (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | \ 35 MMC_RSP_BUSY) 36 #define MMC_RSP_R2 (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC) 37 #define MMC_RSP_R3 (MMC_RSP_PRESENT) 38 #define MMC_RSP_R4 (MMC_RSP_PRESENT) 39 #define MMC_RSP_R5 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE) 40 #define MMC_RSP_R6 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE) 41 #define MMC_RSP_R7 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE) 42 43 #define SDHCI_DMA_ADDRESS 0x00 44 #define SDHCI_BLOCK_SIZE 0x04 45 #define SDHCI_MAKE_BLKSZ(dma, blksz) ((((dma) & 0x7) << 12) | ((blksz) & 0xFFF)) 46 #define SDHCI_BLOCK_COUNT 0x06 47 #define SDHCI_ARGUMENT 0x08 48 #define SDHCI_TRANSFER_MODE 0x0C 49 #define SDHCI_TRNS_DMA BIT(0) 50 #define SDHCI_TRNS_BLK_CNT_EN BIT(1) 51 #define SDHCI_TRNS_ACMD12 BIT(2) 52 #define SDHCI_TRNS_READ BIT(4) 53 #define SDHCI_TRNS_MULTI BIT(5) 54 #define SDHCI_COMMAND 0x0E 55 #define SDHCI_CMD_RESP_MASK 0x03 56 #define SDHCI_CMD_CRC 0x08 57 #define SDHCI_CMD_INDEX 0x10 58 #define SDHCI_CMD_DATA 0x20 59 #define SDHCI_CMD_ABORTCMD 0xC0 60 #define SDHCI_CMD_RESP_NONE 0x00 61 #define SDHCI_CMD_RESP_LONG 0x01 62 #define SDHCI_CMD_RESP_SHORT 0x02 63 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 64 #define SDHCI_MAKE_CMD(c, f) ((((c) & 0xff) << 8) | ((f) & 0xff)) 65 #define SDHCI_RESPONSE 0x10 66 #define SDHCI_HOST_CONTROL 0x28 67 #define SDHCI_CTRL_DMA_MASK 0x18 68 #define SDHCI_CTRL_SDMA 0x00 69 #define SDHCI_BLOCK_GAP_CONTROL 0x2A 70 #define SDHCI_SOFTWARE_RESET 0x2F 71 #define SDHCI_RESET_CMD 0x02 72 #define SDHCI_RESET_DATA 0x04 73 #define SDHCI_INT_STATUS 0x30 74 #define SDHCI_INT_RESPONSE BIT(0) 75 #define SDHCI_INT_DATA_END BIT(1) 76 #define SDHCI_INT_DMA_END BIT(3) 77 #define SDHCI_INT_ERROR BIT(15) 78 #define SDHCI_SIGNAL_ENABLE 0x38 79 80 /* RCA assigned by Boot ROM */ 81 #define UNIPHIER_EMMC_RCA 0x1000 82 83 struct uniphier_mmc_cmd { 84 unsigned int cmdidx; 85 unsigned int resp_type; 86 unsigned int cmdarg; 87 unsigned int is_data; 88 }; 89 90 struct uniphier_emmc_host { 91 uintptr_t base; 92 bool is_block_addressing; 93 }; 94 95 static struct uniphier_emmc_host uniphier_emmc_host; 96 97 static int uniphier_emmc_send_cmd(uintptr_t host_base, 98 struct uniphier_mmc_cmd *cmd) 99 { 100 uint32_t mode = 0; 101 uint32_t end_bit; 102 uint32_t stat, flags, dma_addr; 103 104 mmio_write_32(host_base + SDHCI_INT_STATUS, -1); 105 mmio_write_32(host_base + SDHCI_SIGNAL_ENABLE, 0); 106 mmio_write_32(host_base + SDHCI_ARGUMENT, cmd->cmdarg); 107 108 if (cmd->is_data) 109 mode = SDHCI_TRNS_DMA | SDHCI_TRNS_BLK_CNT_EN | 110 SDHCI_TRNS_ACMD12 | SDHCI_TRNS_READ | 111 SDHCI_TRNS_MULTI; 112 113 mmio_write_16(host_base + SDHCI_TRANSFER_MODE, mode); 114 115 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 116 flags = SDHCI_CMD_RESP_NONE; 117 else if (cmd->resp_type & MMC_RSP_136) 118 flags = SDHCI_CMD_RESP_LONG; 119 else if (cmd->resp_type & MMC_RSP_BUSY) 120 flags = SDHCI_CMD_RESP_SHORT_BUSY; 121 else 122 flags = SDHCI_CMD_RESP_SHORT; 123 124 if (cmd->resp_type & MMC_RSP_CRC) 125 flags |= SDHCI_CMD_CRC; 126 if (cmd->resp_type & MMC_RSP_OPCODE) 127 flags |= SDHCI_CMD_INDEX; 128 if (cmd->is_data) 129 flags |= SDHCI_CMD_DATA; 130 131 if (cmd->resp_type & MMC_RSP_BUSY || cmd->is_data) 132 end_bit = SDHCI_INT_DATA_END; 133 else 134 end_bit = SDHCI_INT_RESPONSE; 135 136 mmio_write_16(host_base + SDHCI_COMMAND, 137 SDHCI_MAKE_CMD(cmd->cmdidx, flags)); 138 139 do { 140 stat = mmio_read_32(host_base + SDHCI_INT_STATUS); 141 if (stat & SDHCI_INT_ERROR) 142 return -EIO; 143 144 if (stat & SDHCI_INT_DMA_END) { 145 mmio_write_32(host_base + SDHCI_INT_STATUS, stat); 146 dma_addr = mmio_read_32(host_base + SDHCI_DMA_ADDRESS); 147 mmio_write_32(host_base + SDHCI_DMA_ADDRESS, dma_addr); 148 } 149 } while (!(stat & end_bit)); 150 151 return 0; 152 } 153 154 static int uniphier_emmc_switch_part(uintptr_t host_base, int part_num) 155 { 156 struct uniphier_mmc_cmd cmd = {0}; 157 158 cmd.cmdidx = MMC_CMD_SWITCH; 159 cmd.resp_type = MMC_RSP_R1b; 160 cmd.cmdarg = (EXT_CSD_PART_CONF << 16) | (part_num << 8) | (3 << 24); 161 162 return uniphier_emmc_send_cmd(host_base, &cmd); 163 } 164 165 static int uniphier_emmc_check_device_size(uintptr_t host_base, 166 bool *is_block_addressing) 167 { 168 struct uniphier_mmc_cmd cmd = {0}; 169 uint32_t csd40, csd72; /* CSD[71:40], CSD[103:72] */ 170 int ret; 171 172 cmd.cmdidx = MMC_CMD_SEND_CSD; 173 cmd.resp_type = MMC_RSP_R2; 174 cmd.cmdarg = UNIPHIER_EMMC_RCA << 16; 175 176 ret = uniphier_emmc_send_cmd(host_base, &cmd); 177 if (ret) 178 return ret; 179 180 csd40 = mmio_read_32(host_base + SDHCI_RESPONSE + 4); 181 csd72 = mmio_read_32(host_base + SDHCI_RESPONSE + 8); 182 183 /* C_SIZE == 0xfff && C_SIZE_MULT == 0x7 ? */ 184 *is_block_addressing = !(~csd40 & 0xffc00380) && !(~csd72 & 0x3); 185 186 return 0; 187 } 188 189 static int uniphier_emmc_load_image(uintptr_t host_base, 190 uint32_t dev_addr, 191 unsigned long load_addr, 192 uint32_t block_cnt) 193 { 194 struct uniphier_mmc_cmd cmd = {0}; 195 uint8_t tmp; 196 197 assert((load_addr >> 32) == 0); 198 199 mmio_write_32(host_base + SDHCI_DMA_ADDRESS, load_addr); 200 mmio_write_16(host_base + SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(7, 512)); 201 mmio_write_16(host_base + SDHCI_BLOCK_COUNT, block_cnt); 202 203 tmp = mmio_read_8(host_base + SDHCI_HOST_CONTROL); 204 tmp &= ~SDHCI_CTRL_DMA_MASK; 205 tmp |= SDHCI_CTRL_SDMA; 206 mmio_write_8(host_base + SDHCI_HOST_CONTROL, tmp); 207 208 tmp = mmio_read_8(host_base + SDHCI_BLOCK_GAP_CONTROL); 209 tmp &= ~1; /* clear Stop At Block Gap Request */ 210 mmio_write_8(host_base + SDHCI_BLOCK_GAP_CONTROL, tmp); 211 212 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; 213 cmd.resp_type = MMC_RSP_R1; 214 cmd.cmdarg = dev_addr; 215 cmd.is_data = 1; 216 217 return uniphier_emmc_send_cmd(host_base, &cmd); 218 } 219 220 static size_t uniphier_emmc_read(int lba, uintptr_t buf, size_t size) 221 { 222 int ret; 223 224 inv_dcache_range(buf, size); 225 226 if (!uniphier_emmc_host.is_block_addressing) 227 lba *= 512; 228 229 ret = uniphier_emmc_load_image(uniphier_emmc_host.base, 230 lba, buf, size / 512); 231 232 inv_dcache_range(buf, size); 233 234 return ret ? 0 : size; 235 } 236 237 static struct io_block_dev_spec uniphier_emmc_dev_spec = { 238 .ops = { 239 .read = uniphier_emmc_read, 240 }, 241 .block_size = 512, 242 }; 243 244 static int uniphier_emmc_hw_init(struct uniphier_emmc_host *host) 245 { 246 struct uniphier_mmc_cmd cmd = {0}; 247 uintptr_t host_base = uniphier_emmc_host.base; 248 int ret; 249 250 /* 251 * deselect card before SEND_CSD command. 252 * Do not check the return code. It fails, but it is OK. 253 */ 254 cmd.cmdidx = MMC_CMD_SELECT_CARD; 255 cmd.resp_type = MMC_RSP_R1; 256 257 uniphier_emmc_send_cmd(host_base, &cmd); /* CMD7 (arg=0) */ 258 259 /* reset CMD Line */ 260 mmio_write_8(host_base + SDHCI_SOFTWARE_RESET, 261 SDHCI_RESET_CMD | SDHCI_RESET_DATA); 262 while (mmio_read_8(host_base + SDHCI_SOFTWARE_RESET)) 263 ; 264 265 ret = uniphier_emmc_check_device_size(host_base, 266 &uniphier_emmc_host.is_block_addressing); 267 if (ret) 268 return ret; 269 270 cmd.cmdarg = UNIPHIER_EMMC_RCA << 16; 271 272 /* select card again */ 273 ret = uniphier_emmc_send_cmd(host_base, &cmd); 274 if (ret) 275 return ret; 276 277 /* switch to Boot Partition 1 */ 278 ret = uniphier_emmc_switch_part(host_base, 1); 279 if (ret) 280 return ret; 281 282 return 0; 283 } 284 285 static const uintptr_t uniphier_emmc_base[] = { 286 [UNIPHIER_SOC_LD11] = 0x5a000200, 287 [UNIPHIER_SOC_LD20] = 0x5a000200, 288 [UNIPHIER_SOC_PXS3] = 0x5a000200, 289 }; 290 291 int uniphier_emmc_init(unsigned int soc, 292 struct io_block_dev_spec **block_dev_spec) 293 { 294 int ret; 295 296 assert(soc < ARRAY_SIZE(uniphier_emmc_base)); 297 uniphier_emmc_host.base = uniphier_emmc_base[soc]; 298 if (uniphier_emmc_host.base == 0UL) 299 return -ENOTSUP; 300 301 ret = uniphier_emmc_hw_init(&uniphier_emmc_host); 302 if (ret) 303 return ret; 304 305 *block_dev_spec = &uniphier_emmc_dev_spec; 306 307 return 0; 308 } 309