1*ac9f1b55SMasahiro Yamada /* 2*ac9f1b55SMasahiro Yamada * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3*ac9f1b55SMasahiro Yamada * 4*ac9f1b55SMasahiro Yamada * SPDX-License-Identifier: BSD-3-Clause 5*ac9f1b55SMasahiro Yamada */ 6*ac9f1b55SMasahiro Yamada 7*ac9f1b55SMasahiro Yamada #ifndef UNIPHIER_CONSOLE_H 8*ac9f1b55SMasahiro Yamada #define UNIPHIER_CONSOLE_H 9*ac9f1b55SMasahiro Yamada 10*ac9f1b55SMasahiro Yamada #define UNIPHIER_UART_RX 0x00 /* In: Receive buffer */ 11*ac9f1b55SMasahiro Yamada #define UNIPHIER_UART_TX 0x00 /* Out: Transmit buffer */ 12*ac9f1b55SMasahiro Yamada 13*ac9f1b55SMasahiro Yamada #define UNIPHIER_UART_FCR 0x0c /* Char/FIFO Control Register */ 14*ac9f1b55SMasahiro Yamada #define UNIPHIER_UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ 15*ac9f1b55SMasahiro Yamada 16*ac9f1b55SMasahiro Yamada #define UNIPHIER_UART_LCR_MCR 0x10 /* Line/Modem Control Register */ 17*ac9f1b55SMasahiro Yamada #define UNIPHIER_UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ 18*ac9f1b55SMasahiro Yamada #define UNIPHIER_UART_LSR 0x14 /* Line Status Register */ 19*ac9f1b55SMasahiro Yamada #define UNIPHIER_UART_LSR_TEMT 0x40 /* Transmitter empty */ 20*ac9f1b55SMasahiro Yamada #define UNIPHIER_UART_LSR_TEMT_BIT 6 /* Transmitter empty */ 21*ac9f1b55SMasahiro Yamada #define UNIPHIER_UART_LSR_THRE_BIT 5 /* Transmit-hold-register empty */ 22*ac9f1b55SMasahiro Yamada #define UNIPHIER_UART_LSR_DR_BIT 0 /* Receiver data ready */ 23*ac9f1b55SMasahiro Yamada #define UNIPHIER_UART_DLR 0x24 /* Divisor Latch Register */ 24*ac9f1b55SMasahiro Yamada 25*ac9f1b55SMasahiro Yamada #endif /* UNIPHIER_CONSOLE_H */ 26