xref: /rk3399_ARM-atf/plat/socionext/uniphier/uniphier_bl31_setup.c (revision c948f77136c42a92d0bb660543a3600c36dcf7f1)
1 /*
2  * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 #include <errno.h>
9 
10 #include <platform_def.h>
11 
12 #include <arch.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <drivers/console.h>
16 #include <lib/mmio.h>
17 #include <lib/xlat_tables/xlat_mmu_helpers.h>
18 #include <plat/common/platform.h>
19 
20 #include "uniphier.h"
21 
22 #define BL31_SIZE		((BL31_END) - (BL31_BASE))
23 
24 static entry_point_info_t bl32_image_ep_info;
25 static entry_point_info_t bl33_image_ep_info;
26 
27 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
28 {
29 	assert(sec_state_is_valid(type));
30 	return type == NON_SECURE ? &bl33_image_ep_info : &bl32_image_ep_info;
31 }
32 
33 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
34 				u_register_t arg2, u_register_t arg3)
35 {
36 	void *from_bl2;
37 
38 	from_bl2 = (void *) arg0;
39 
40 	bl_params_node_t *bl_params = ((bl_params_t *)from_bl2)->head;
41 
42 	uniphier_console_setup();
43 
44 	while (bl_params) {
45 		if (bl_params->image_id == BL32_IMAGE_ID)
46 			bl32_image_ep_info = *bl_params->ep_info;
47 
48 		if (bl_params->image_id == BL33_IMAGE_ID)
49 			bl33_image_ep_info = *bl_params->ep_info;
50 
51 		bl_params = bl_params->next_params_info;
52 	}
53 
54 	if (bl33_image_ep_info.pc == 0)
55 		panic();
56 }
57 
58 #define UNIPHIER_SYS_CNTCTL_BASE	0x60E00000
59 
60 void bl31_platform_setup(void)
61 {
62 	unsigned int soc;
63 
64 	soc = uniphier_get_soc_id();
65 	if (soc == UNIPHIER_SOC_UNKNOWN) {
66 		ERROR("unsupported SoC\n");
67 		plat_error_handler(-ENOTSUP);
68 	}
69 
70 	uniphier_cci_init(soc);
71 	uniphier_cci_enable();
72 
73 	/* Initialize the GIC driver, cpu and distributor interfaces */
74 	uniphier_gic_driver_init(soc);
75 	uniphier_gic_init();
76 
77 	/* Enable and initialize the System level generic timer */
78 	mmio_write_32(UNIPHIER_SYS_CNTCTL_BASE + CNTCR_OFF,
79 			CNTCR_FCREQ(0U) | CNTCR_EN);
80 }
81 
82 void bl31_plat_arch_setup(void)
83 {
84 	uniphier_mmap_setup(BL31_BASE, BL31_SIZE, NULL);
85 	enable_mmu_el3(0);
86 }
87 
88 void bl31_plat_runtime_setup(void)
89 {
90 	/* Suppress any runtime logs unless DEBUG is defined */
91 #if !DEBUG
92 	console_uninit();
93 #endif
94 }
95