1 /* 2 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <platform_def.h> 11 12 #include <arch.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/console.h> 16 #include <lib/mmio.h> 17 #include <plat/common/platform.h> 18 19 #include "uniphier.h" 20 21 static entry_point_info_t bl32_image_ep_info; 22 static entry_point_info_t bl33_image_ep_info; 23 static unsigned int uniphier_soc = UNIPHIER_SOC_UNKNOWN; 24 25 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 26 { 27 assert(sec_state_is_valid(type)); 28 return type == NON_SECURE ? &bl33_image_ep_info : &bl32_image_ep_info; 29 } 30 31 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 32 u_register_t arg2, u_register_t arg3) 33 { 34 void *from_bl2; 35 36 from_bl2 = (void *)arg0; 37 38 bl_params_node_t *bl_params = ((bl_params_t *)from_bl2)->head; 39 40 uniphier_soc = uniphier_get_soc_id(); 41 if (uniphier_soc == UNIPHIER_SOC_UNKNOWN) 42 plat_error_handler(-ENOTSUP); 43 44 uniphier_console_setup(uniphier_soc); 45 46 while (bl_params) { 47 if (bl_params->image_id == BL32_IMAGE_ID) 48 bl32_image_ep_info = *bl_params->ep_info; 49 50 if (bl_params->image_id == BL33_IMAGE_ID) 51 bl33_image_ep_info = *bl_params->ep_info; 52 53 bl_params = bl_params->next_params_info; 54 } 55 56 if (bl33_image_ep_info.pc == 0) 57 panic(); 58 } 59 60 static const uintptr_t uniphier_cntctl_base[] = { 61 [UNIPHIER_SOC_LD11] = 0x60e00000, 62 [UNIPHIER_SOC_LD20] = 0x60e00000, 63 [UNIPHIER_SOC_PXS3] = 0x60e00000, 64 }; 65 66 void bl31_platform_setup(void) 67 { 68 uintptr_t cntctl_base; 69 70 uniphier_cci_init(uniphier_soc); 71 uniphier_cci_enable(); 72 73 /* Initialize the GIC driver, cpu and distributor interfaces */ 74 uniphier_gic_driver_init(uniphier_soc); 75 uniphier_gic_init(); 76 77 assert(uniphier_soc < ARRAY_SIZE(uniphier_cntctl_base)); 78 cntctl_base = uniphier_cntctl_base[uniphier_soc]; 79 80 /* Enable and initialize the System level generic timer */ 81 mmio_write_32(cntctl_base + CNTCR_OFF, CNTCR_FCREQ(0U) | CNTCR_EN); 82 83 uniphier_psci_init(uniphier_soc); 84 } 85 86 void bl31_plat_arch_setup(void) 87 { 88 uniphier_mmap_setup(uniphier_soc); 89 } 90